|
| union { |
| uint32_t command |
| |
| struct { |
| uint32_t run_stop: 1 |
| | 1=Run. 0=Stop More...
|
| |
| uint32_t reset: 1 |
| | SW write 1 to reset HC, clear by HC when complete. More...
|
| |
| uint32_t framelist_size: 2 |
| | Frame List size 0: 1024, 1: 512, 2: 256. More...
|
| |
| uint32_t periodic_enable: 1 |
| | This bit controls whether the host controller skips processing the Periodic Schedule. Values mean: 0b Do not process the Periodic Schedule 1b Use the PERIODICLISTBASE register to access the Periodic Schedule. More...
|
| |
| uint32_t async_enable: 1 |
| | This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean: 0b Do not process the Asynchronous Schedule 1b Use the ASYNCLISTADDR register to access the Asynchronous Schedule. More...
|
| |
| uint32_t async_adv_doorbell: 1 |
| | Tell HC to interrupt next time it advances async list. Clear by HC. More...
|
| |
| uint32_t light_reset: 1 |
| | Reset HC without affecting ports state. More...
|
| |
| uint32_t async_park_count: 2 |
| | not used by tinyusb More...
|
| |
| uint32_t __pad0__: 1 |
| |
| uint32_t async_park_enable: 1 |
| | Enable park mode, not used by tinyusb. More...
|
| |
| uint32_t __pad1__: 3 |
| |
| uint32_t nxp_framelist_size_msb: 1 |
| | NXP customized : Bit 2 of the Frame List Size bits
011b: 128 elements
100b: 64 elements
101b: 32 elements
110b: 16 elements
111b: 8 elements. More...
|
| |
| uint32_t int_threshold: 8 |
| | Default 08h. Interrupt rate in unit of micro frame. More...
|
| |
| } command_bm |
| |
| }; | |
| |
| union { |
| uint32_t status |
| |
| struct { |
| uint32_t usb: 1 |
| | qTD with IOC is retired More...
|
| |
| uint32_t usb_error: 1 |
| | qTD retired due to error More...
|
| |
| uint32_t port_change_detect: 1 |
| | Set when PortOwner or ForcePortResume change from 0 -> 1. More...
|
| |
| uint32_t framelist_rollover: 1 |
| | R/WC The Host Controller sets this bit to a one when the Frame List Index(see Section 2.3.4) rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Sizefield of the USBCMD register) is 1024, the Frame Index Registerrolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles. More...
|
| |
| uint32_t pci_host_system_error: 1 |
| | R/WC (not used by NXP) The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. More...
|
| |
| uint32_t async_adv: 1 |
| | Async Advance interrupt. More...
|
| |
| uint32_t __pad0__: 1 |
| |
| uint32_t nxp_int_sof: 1 |
| | NXP customized: this bit will be set every 125us and can be used by host controller driver as a time base. More...
|
| |
| uint32_t __pad1__: 4 |
| |
| uint32_t hc_halted: 1 |
| | Opposite value to run_stop bit. More...
|
| |
| uint32_t reclamation: 1 |
| | Used to detect empty async shecudle. More...
|
| |
| uint32_t periodic_status: 1 |
| | Periodic schedule status. More...
|
| |
| uint32_t async_status: 1 |
| | Async schedule status. More...
|
| |
| uint32_t __pad2__: 2 |
| |
| uint32_t nxp_int_async: 1 |
| | NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. More...
|
| |
| uint32_t nxp_int_period: 1 |
| | NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. More...
|
| |
| uint32_t __pad3__: 12 |
| |
| } status_bm |
| |
| }; | |
| |
| union { |
| uint32_t inten |
| |
| struct { |
| uint32_t usb: 1 |
| |
| uint32_t usb_error: 1 |
| |
| uint32_t port_change_detect: 1 |
| |
| uint32_t framelist_rollover: 1 |
| |
| uint32_t pci_host_system_error: 1 |
| |
| uint32_t async_adv: 1 |
| |
| uint32_t __pad0__: 1 |
| |
| uint32_t nxp_int_sof: 1 |
| |
| uint32_t __pad1__: 10 |
| |
| uint32_t nxp_int_async: 1 |
| |
| uint32_t nxp_int_period: 1 |
| |
| uint32_t __pad2__: 12 |
| |
| } inten_bm |
| |
| }; | |
| |
| uint32_t | frame_index |
| | 0x0C Micro frame counter More...
|
| |
| uint32_t | ctrl_ds_seg |
| | 0x10 Control Data Structure Segment More...
|
| |
| uint32_t | periodic_list_base |
| | 0x14 Beginning address of perodic frame list More...
|
| |
| uint32_t | async_list_addr |
| | 0x18 Address of next async QHD to be executed More...
|
| |
| uint32_t | nxp_tt_control |
| | nxp embedded transaction translator (reserved by EHCI specs) More...
|
| |
| uint32_t | reserved [8] |
| |
| uint32_t | config_flag |
| | 0x40 not used by NXP More...
|
| |
| union { |
| uint32_t portsc |
| | 0x44 port status and control More...
|
| |
| struct { |
| uint32_t current_connect_status: 1 |
| | 00: 0: No device, 1: Device is present on port More...
|
| |
| uint32_t connect_status_change: 1 |
| | 01: [R/WC] Change in Current Connect Status More...
|
| |
| uint32_t port_enabled: 1 |
| | 02: Ports can only be enabled by HC as a part of the reset and enable. SW can write 0 to disable More...
|
| |
| uint32_t port_enable_change: 1 |
| | 03: [R/WC] Port Enabled has changed More...
|
| |
| uint32_t over_current_active: 1 |
| | 04: Port has an over-current condition More...
|
| |
| uint32_t over_current_change: 1 |
| | 05: [R/WC] Change to Over-current Active More...
|
| |
| uint32_t force_port_resume: 1 |
| | 06: Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit. More...
|
| |
| uint32_t suspend: 1 |
| | 07: Port in suspend state More...
|
| |
| uint32_t port_reset: 1 |
| | 08: 1=Port is in Reset. 0=Port is not in Reset More...
|
| |
| uint32_t nxp_highspeed_status: 1 |
| | 09: NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode More...
|
| |
| uint32_t line_status: 2 |
| | 10-11: D+/D- state: 00: SE0, 10: J-state, 01: K-state More...
|
| |
| uint32_t port_power: 1 |
| | 12: 0= power off, 1= power on More...
|
| |
| uint32_t port_owner: 1 |
| | 13: not used by NXP More...
|
| |
| uint32_t port_indicator_control: 2 |
| | 14-15: 00b: off, 01b: Amber, 10b: green, 11b: undefined More...
|
| |
| uint32_t port_test_control: 4 |
| | 16-19: Port test mode, not used by tinyusb More...
|
| |
| uint32_t wake_on_connect_enable: 1 |
| | 20: Enables device connects as wake-up events More...
|
| |
| uint32_t wake_on_disconnect_enable: 1 |
| | 21: Enables device disconnects as wake-up events More...
|
| |
| uint32_t wake_on_over_current_enable: 1 |
| | 22: Enables over-current conditions as wake-up events More...
|
| |
| uint32_t nxp_phy_clock_disable: 1 |
| | 23: NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock More...
|
| |
| uint32_t nxp_port_force_fullspeed: 1 |
| | 24: NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. More...
|
| |
| uint32_t TU_RESERVED: 1 |
| | 25 More...
|
| |
| uint32_t nxp_port_speed: 2 |
| | 26-27: NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed More...
|
| |
| } portsc_bm |
| |
| }; | |
| |
Definition at line 318 of file ehci.h.
1.9.2