|
| enum | { OHCI_CONTROL_FUNCSTATE_RESET = 0
, OHCI_CONTROL_FUNCSTATE_RESUME
, OHCI_CONTROL_FUNCSTATE_OPERATIONAL
, OHCI_CONTROL_FUNCSTATE_SUSPEND
} |
| |
| enum | {
OHCI_CONTROL_CONTROL_BULK_RATIO = 3
, OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK = TU_BIT(2)
, OHCI_CONTROL_LIST_ISOCHRONOUS_ENABLE_MASK = TU_BIT(3)
, OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK = TU_BIT(4)
,
OHCI_CONTROL_LIST_BULK_ENABLE_MASK = TU_BIT(5)
} |
| |
| enum | { OHCI_FMINTERVAL_FI = 0x2EDF
, OHCI_FMINTERVAL_FSMPS = (6*(OHCI_FMINTERVAL_FI-210)) / 7
} |
| |
| enum | { OHCI_PERIODIC_START = 0x3E67
} |
| |
| enum | {
OHCI_INT_SCHEDULING_OVERUN_MASK = TU_BIT(0)
, OHCI_INT_WRITEBACK_DONEHEAD_MASK = TU_BIT(1)
, OHCI_INT_SOF_MASK = TU_BIT(2)
, OHCI_INT_RESUME_DETECTED_MASK = TU_BIT(3)
,
OHCI_INT_UNRECOVERABLE_ERROR_MASK = TU_BIT(4)
, OHCI_INT_FRAME_OVERFLOW_MASK = TU_BIT(5)
, OHCI_INT_RHPORT_STATUS_CHANGE_MASK = TU_BIT(6)
, OHCI_INT_OWNERSHIP_CHANGE_MASK = TU_BIT(30)
,
OHCI_INT_MASTER_ENABLE_MASK = TU_BIT(31)
} |
| |
| enum | {
RHPORT_CURRENT_CONNECT_STATUS_MASK = TU_BIT(0)
, RHPORT_PORT_ENABLE_STATUS_MASK = TU_BIT(1)
, RHPORT_PORT_SUSPEND_STATUS_MASK = TU_BIT(2)
, RHPORT_PORT_OVER_CURRENT_INDICATOR_MASK = TU_BIT(3)
,
RHPORT_PORT_RESET_STATUS_MASK = TU_BIT(4)
, RHPORT_PORT_POWER_STATUS_MASK = TU_BIT(8)
, RHPORT_LOW_SPEED_DEVICE_ATTACHED_MASK = TU_BIT(9)
, RHPORT_CONNECT_STATUS_CHANGE_MASK = TU_BIT(16)
,
RHPORT_PORT_ENABLE_CHANGE_MASK = TU_BIT(17)
, RHPORT_PORT_SUSPEND_CHANGE_MASK = TU_BIT(18)
, RHPORT_OVER_CURRENT_CHANGE_MASK = TU_BIT(19)
, RHPORT_PORT_RESET_CHANGE_MASK = TU_BIT(20)
,
RHPORT_ALL_CHANGE_MASK
} |
| |
| enum | {
OHCI_CCODE_NO_ERROR = 0
, OHCI_CCODE_CRC = 1
, OHCI_CCODE_BIT_STUFFING = 2
, OHCI_CCODE_DATA_TOGGLE_MISMATCH = 3
,
OHCI_CCODE_STALL = 4
, OHCI_CCODE_DEVICE_NOT_RESPONDING = 5
, OHCI_CCODE_PID_CHECK_FAILURE = 6
, OHCI_CCODE_UNEXPECTED_PID = 7
,
OHCI_CCODE_DATA_OVERRUN = 8
, OHCI_CCODE_DATA_UNDERRUN = 9
, OHCI_CCODE_BUFFER_OVERRUN = 12
, OHCI_CCODE_BUFFER_UNDERRUN = 13
,
OHCI_CCODE_NOT_ACCESSED = 14
} |
| |
| enum | { OHCI_INT_ON_COMPLETE_YES = 0
, OHCI_INT_ON_COMPLETE_NO = TU_BIN8(111)
} |
| |
| enum | { GTD_DT_TOGGLE_CARRY = 0
, GTD_DT_DATA0 = TU_BIT(1) | 0
, GTD_DT_DATA1 = TU_BIT(1) | 1
} |
| |
| enum | { PID_SETUP = 0
, PID_OUT
, PID_IN
} |
| |
| enum | { PID_FROM_TD = 0
} |
| |
|
| CFG_TUH_MEM_SECTION | TU_ATTR_ALIGNED (256) |
| |
| static void | ed_list_insert (ohci_ed_t *p_pre, ohci_ed_t *p_ed) |
| |
| static void | ed_list_remove_by_addr (ohci_ed_t *p_head, uint8_t dev_addr) |
| |
| static gtd_extra_data_t * | gtd_get_extra_data (ohci_gtd_t const *const gtd) |
| |
| static TU_ATTR_ALWAYS_INLINE void * | _phys_addr (void *virtual_address) |
| |
| static TU_ATTR_ALWAYS_INLINE void * | _virt_addr (void *physical_address) |
| |
| bool | hcd_init (uint8_t rhport, const tusb_rhport_init_t *rh_init) |
| |
| uint32_t | hcd_frame_number (uint8_t rhport) |
| |
| void | hcd_port_reset (uint8_t hostid) |
| |
| void | hcd_port_reset_end (uint8_t rhport) |
| |
| bool | hcd_port_connect_status (uint8_t hostid) |
| |
| tusb_speed_t | hcd_port_speed_get (uint8_t hostid) |
| |
| void | hcd_device_close (uint8_t rhport, uint8_t dev_addr) |
| |
| static tusb_xfer_type_t | ed_get_xfer_type (ohci_ed_t const *const p_ed) |
| |
| static void | ed_init (ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t ep_size, uint8_t ep_addr, uint8_t xfer_type, uint8_t interval) |
| |
| static void | gtd_init (ohci_gtd_t *p_td, uint8_t *data_ptr, uint16_t total_bytes) |
| |
| static ohci_ed_t * | ed_from_addr (uint8_t dev_addr, uint8_t ep_addr) |
| |
| static ohci_ed_t * | ed_find_free (void) |
| |
| static ohci_gtd_t * | gtd_find_free (void) |
| |
| static void | td_insert_to_ed (ohci_ed_t *p_ed, ohci_gtd_t *p_gtd) |
| |
| bool | hcd_edpt_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc) |
| |
| bool | hcd_setup_send (uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) |
| |
| bool | hcd_edpt_xfer (uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) |
| |
| bool | hcd_edpt_abort_xfer (uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) |
| |
| bool | hcd_edpt_clear_stall (uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) |
| |
| static ohci_td_item_t * | list_reverse (ohci_td_item_t *td_head) |
| |
| static bool | gtd_is_control (ohci_gtd_t const *const p_qtd) |
| |
| static ohci_ed_t * | gtd_get_ed (ohci_gtd_t const *const p_qtd) |
| |
| static uint32_t | gtd_xfer_byte_left (uint32_t buffer_end, uint32_t current_buffer) |
| |
| static void | done_queue_isr (uint8_t hostid) |
| |
| void | hcd_int_handler (uint8_t hostid, bool in_isr) |
| |
1.9.2