Open FFBoard
Open source force feedback firmware
rusb2_type.h
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1/*
2 * The MIT License (MIT)
3 *
4 * Copyright (c) 2022 Rafael Silva (@perigoso)
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 *
24 * This file is part of the TinyUSB stack.
25 */
26
27#ifndef _TUSB_RUSB2_TYPE_H_
28#define _TUSB_RUSB2_TYPE_H_
29
30#include <stdint.h>
31#include <stddef.h>
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37// CCRX specific attribute to generate a Code that Accesses Variables in the Declared Size
38#ifdef __CCRX__
39 #define _ccrx_evenaccess __evenaccess
40#else
41 #define _ccrx_evenaccess
42#endif
43
44/*--------------------------------------------------------------------*/
45/* Register Definitions */
46/*--------------------------------------------------------------------*/
47
48/* Start of definition of packed structs (used by the CCRX toolchain) */
49TU_ATTR_PACKED_BEGIN
50TU_ATTR_BIT_FIELD_ORDER_BEGIN
51
52// TODO same as RUSB2_PIPE_TR_t
53typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
54 union {
55 struct {
56 uint16_t : 8;
57 uint16_t TRCLR: 1;
58 uint16_t TRENB: 1;
59 uint16_t : 0;
60 };
61 uint16_t TRE;
62 };
63 uint16_t TRN;
64} reg_pipetre_t;
65
66typedef struct {
67 union {
68 volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
69
70 struct TU_ATTR_PACKED {
71 uint16_t : 8;
72 volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
73 volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
74 uint16_t : 6;
75 } E_b;
76 };
77
78 union {
79 volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */
80
81 struct TU_ATTR_PACKED {
82 volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */
83 } N_b;
84 };
85} RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */
86
87
88/* RUSB2 Registers Structure */
89typedef struct _ccrx_evenaccess {
90 union {
91 volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
92
93 struct TU_ATTR_PACKED {
94 volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */
95 uint16_t : 2;
96 volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */
97 volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
98 volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */
99 volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */
100 volatile uint16_t HSE : 1; // [7..7] High-Speed Operation Enable
101 volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */
102 uint16_t : 1;
103 volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */
104 uint16_t : 5;
105 } SYSCFG_b;
106 };
107
108 union {
109 volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */
110
111 struct TU_ATTR_PACKED {
112 volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
113 uint16_t : 12;
114 } BUSWAIT_b;
115 };
116
117 union {
118 volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */
119
120 struct TU_ATTR_PACKED {
121 volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */
122 volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */
123 uint16_t : 2;
124 volatile const uint16_t SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
125 volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */
126 uint16_t : 7;
127 volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
128 } SYSSTS0_b;
129 };
130
131 union {
132 volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */
133
134 struct TU_ATTR_PACKED {
135 volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
136 uint16_t : 15;
137 } PLLSTA_b;
138 };
139
140 union {
141 volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */
142
143 struct TU_ATTR_PACKED {
144 volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */
145 uint16_t : 1;
146 volatile uint16_t UACT : 1; /* [4..4] USB Bus Enable */
147 volatile uint16_t RESUME : 1; /* [5..5] Resume Output */
148 volatile uint16_t USBRST : 1; /* [6..6] USB Bus Reset Output */
149 volatile uint16_t RWUPE : 1; /* [7..7] Wakeup Detection Enable */
150 volatile uint16_t WKUP : 1; /* [8..8] Wakeup Output */
151 volatile uint16_t VBUSEN : 1; /* [9..9] USB_VBUSEN Output Pin Control */
152 volatile uint16_t EXICEN : 1; /* [10..10] USB_EXICEN Output Pin Control */
153 volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */
154 uint16_t : 4;
155 } DVSTCTR0_b;
156 };
157 volatile const uint16_t RESERVED;
158
159 union {
160 volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */
161
162 struct TU_ATTR_PACKED {
163 volatile uint16_t UTST : 4; /* [3..0] Test Mode */
164 uint16_t : 12;
165 } TESTMODE_b;
166 };
167 volatile const uint16_t RESERVED1;
168 volatile const uint32_t RESERVED2;
169
170 union {
171 volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */
172
173 struct TU_ATTR_PACKED {
174 union {
175 volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */
176 volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */
177 };
178
179 union {
180 volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */
181
182 struct TU_ATTR_PACKED {
183 volatile const uint8_t RESERVED3;
184 volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */
185 };
186 };
187 };
188 };
189
190 union {
191 volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */
192
193 struct TU_ATTR_PACKED {
194 union {
195 volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */
196 volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */
197 };
198
199 union {
200 volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */
201
202 struct TU_ATTR_PACKED {
203 volatile const uint8_t RESERVED4;
204 volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */
205 };
206 };
207 };
208 };
209
210 union {
211 volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */
212
213 struct TU_ATTR_PACKED {
214 union {
215 volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */
216 volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */
217 };
218
219 union {
220 volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */
221
222 struct TU_ATTR_PACKED {
223 volatile const uint8_t RESERVED5;
224 volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */
225 };
226 };
227 };
228 };
229
230 union {
231 volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */
232
233 struct TU_ATTR_PACKED {
234 volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */
235 uint16_t : 1;
236 volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */
237 uint16_t : 2;
238 volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */
239 uint16_t : 1;
240 volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */
241 uint16_t : 2;
242 volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */
243 volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
244 } CFIFOSEL_b;
245 };
246
247 union {
248 volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */
249
250 struct TU_ATTR_PACKED {
251 volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
252 uint16_t : 1;
253 volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
254 volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
255 volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */
256 } CFIFOCTR_b;
257 };
258 volatile const uint32_t RESERVED6;
259
260 union {
261 volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */
262
263 struct TU_ATTR_PACKED {
264 volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
265 uint16_t : 4;
266 volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
267 uint16_t : 1;
268 volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */
269 volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
270 volatile uint16_t DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
271 volatile uint16_t REW : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
272 volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
273 } D0FIFOSEL_b;
274 };
275
276 union {
277 volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */
278
279 struct TU_ATTR_PACKED {
280 volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
281 uint16_t : 1;
282 volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
283 volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
284 volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */
285 } D0FIFOCTR_b;
286 };
287
288 union {
289 volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */
290
291 struct TU_ATTR_PACKED {
292 volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
293 uint16_t : 4;
294 volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
295 uint16_t : 1;
296 volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */
297 volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
298 volatile uint16_t DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
299 volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */
300 volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
301 } D1FIFOSEL_b;
302 };
303
304 union {
305 volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */
306
307 struct TU_ATTR_PACKED {
308 volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
309 uint16_t : 1;
310 volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
311 volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
312 volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */
313 } D1FIFOCTR_b;
314 };
315
316 union {
317 volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
318
319 struct TU_ATTR_PACKED {
320 uint16_t : 8;
321 volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
322 volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
323 volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
324 volatile uint16_t CTRE : 1; /* [11..11] Control Transfer Stage Transition Interrupt Enable */
325 volatile uint16_t DVSE : 1; /* [12..12] Device State Transition Interrupt Enable */
326 volatile uint16_t SOFE : 1; /* [13..13] Frame Number Update Interrupt Enable */
327 volatile uint16_t RSME : 1; /* [14..14] Resume Interrupt Enable */
328 volatile uint16_t VBSE : 1; /* [15..15] VBUS Interrupt Enable */
329 } INTENB0_b;
330 };
331
332 union {
333 volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */
334
335 struct TU_ATTR_PACKED {
336 volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */
337 uint16_t : 3;
338 volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */
339 volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */
340 volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */
341 uint16_t : 1;
342 volatile uint16_t LPMENDE : 1;
343 volatile uint16_t L1RSMENDE : 1;
344 uint16_t : 1;
345 volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */
346 volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */
347 uint16_t : 1;
348 volatile uint16_t BCHGE : 1; /* [14..14] USB Bus Change Interrupt Enable */
349 volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */
350 } INTENB1_b;
351 };
352 volatile const uint16_t RESERVED7;
353
354 union {
355 volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */
356
357 struct TU_ATTR_PACKED {
358 volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */
359 volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */
360 volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */
361 volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */
362 volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */
363 volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */
364 volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */
365 volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */
366 volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */
367 volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */
368 uint16_t : 6;
369 } BRDYENB_b;
370 };
371
372 union {
373 volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */
374
375 struct TU_ATTR_PACKED {
376 volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */
377 volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */
378 volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */
379 volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */
380 volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */
381 volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */
382 volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */
383 volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */
384 volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */
385 volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */
386 uint16_t : 6;
387 } NRDYENB_b;
388 };
389
390 union {
391 volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */
392
393 struct TU_ATTR_PACKED {
394 volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */
395 volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */
396 volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */
397 volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */
398 volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */
399 volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */
400 volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */
401 volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */
402 volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */
403 volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */
404 uint16_t : 6;
405 } BEMPENB_b;
406 };
407
408 union {
409 volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */
410
411 struct TU_ATTR_PACKED {
412 uint16_t : 4;
413 volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */
414 volatile uint16_t INTL : 1; /* [5..5] Interrupt Output Sense Select */
415 volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */
416 uint16_t : 1;
417 volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */
418 uint16_t : 7;
419 } SOFCFG_b;
420 };
421
422 union {
423 volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */
424
425 struct TU_ATTR_PACKED {
426 volatile uint16_t DIRPD : 1; /* [0..0] Power-Down Control */
427 volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */
428 uint16_t : 1;
429 volatile uint16_t CDPEN : 1; /* [3..3] Charging Downstream Port Enable */
430 volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */
431 uint16_t : 2;
432 volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */
433 uint16_t : 1;
434 volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */
435 uint16_t : 3;
436 volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */
437 } PHYSET_b;
438 };
439
440 union {
441 volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */
442
443 struct TU_ATTR_PACKED {
444 volatile const uint16_t CTSQ : 3; /* [2..0] Control Transfer Stage */
445 volatile uint16_t VALID : 1; /* [3..3] USB Request Reception */
446 volatile const uint16_t DVSQ : 3; /* [6..4] Device State */
447 volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */
448 volatile const uint16_t BRDY : 1; /* [8..8] Buffer Ready Interrupt Status */
449 volatile const uint16_t NRDY : 1; /* [9..9] Buffer Not Ready Interrupt Status */
450 volatile const uint16_t BEMP : 1; /* [10..10] Buffer Empty Interrupt Status */
451 volatile uint16_t CTRT : 1; /* [11..11] Control Transfer Stage Transition Interrupt Status */
452 volatile uint16_t DVST : 1; /* [12..12] Device State Transition Interrupt Status */
453 volatile uint16_t SOFR : 1; /* [13..13] Frame Number Refresh Interrupt Status */
454 volatile uint16_t RESM : 1; /* [14..14] Resume Interrupt Status */
455 volatile uint16_t VBINT : 1; /* [15..15] VBUS Interrupt Status */
456 } INTSTS0_b;
457 };
458
459 union {
460 volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */
461
462 struct TU_ATTR_PACKED {
463 volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */
464 uint16_t : 3;
465 volatile uint16_t SACK : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */
466 volatile uint16_t SIGN : 1; /* [5..5] Setup Transaction Error Interrupt Status */
467 volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */
468 uint16_t : 1;
469 volatile uint16_t LPMEND : 1; /* [8..8] LPM Transaction End Interrupt Status */
470 volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */
471 uint16_t : 1;
472 volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */
473 volatile uint16_t DTCH : 1; /* [12..12] USB Disconnection Detection Interrupt Status */
474 uint16_t : 1;
475 volatile uint16_t BCHG : 1; /* [14..14] USB Bus Change Interrupt Status */
476 volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */
477 } INTSTS1_b;
478 };
479 volatile const uint16_t RESERVED8;
480
481 union {
482 volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */
483
484 struct TU_ATTR_PACKED {
485 volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */
486 volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */
487 volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */
488 volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */
489 volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */
490 volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */
491 volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */
492 volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */
493 volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */
494 volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */
495 uint16_t : 6;
496 } BRDYSTS_b;
497 };
498
499 union {
500 volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */
501
502 struct TU_ATTR_PACKED {
503 volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */
504 volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */
505 volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */
506 volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */
507 volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */
508 volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */
509 volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */
510 volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */
511 volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */
512 volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */
513 uint16_t : 6;
514 } NRDYSTS_b;
515 };
516
517 union {
518 volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */
519
520 struct TU_ATTR_PACKED {
521 volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */
522 volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */
523 volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */
524 volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */
525 volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */
526 volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */
527 volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */
528 volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */
529 volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */
530 volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */
531 uint16_t : 6;
532 } BEMPSTS_b;
533 };
534
535 union {
536 volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */
537
538 struct TU_ATTR_PACKED {
539 volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */
540 uint16_t : 3;
541 volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */
542 volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */
543 } FRMNUM_b;
544 };
545
546 union {
547 volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */
548
549 struct TU_ATTR_PACKED {
550 volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */
551 uint16_t : 12;
552 volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */
553 } UFRMNUM_b;
554 };
555
556 union {
557 volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */
558
559 struct TU_ATTR_PACKED {
560 volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */
561 uint16_t : 1;
562 volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */
563 uint16_t : 5;
564 } USBADDR_b;
565 };
566 volatile const uint16_t RESERVED9;
567
568 union {
569 volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */
570
571 struct TU_ATTR_PACKED {
572 volatile uint16_t BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
573 volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
574 } USBREQ_b;
575 };
576
577 union {
578 volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */
579
580 struct TU_ATTR_PACKED {
581 volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */
582 } USBVAL_b;
583 };
584
585 union {
586 volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */
587
588 struct TU_ATTR_PACKED {
589 volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */
590 } USBINDX_b;
591 };
592
593 union {
594 volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */
595
596 struct TU_ATTR_PACKED {
597 volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */
598 } USBLENG_b;
599 };
600
601 union {
602 volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */
603
604 struct TU_ATTR_PACKED {
605 uint16_t : 4;
606 volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */
607 uint16_t : 2;
608 volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
609 volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */
610 uint16_t : 7;
611 } DCPCFG_b;
612 };
613
614 union {
615 volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */
616
617 struct TU_ATTR_PACKED {
618 volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */
619 uint16_t : 5;
620 volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
621 } DCPMAXP_b;
622 };
623
624 union {
625 volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */
626
627 struct TU_ATTR_PACKED {
628 volatile uint16_t PID : 2; /* [1..0] Response PID */
629 volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */
630 uint16_t : 2;
631 volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
632 volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */
633 volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */
634 volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */
635 uint16_t : 2;
636 volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */
637 volatile uint16_t CSSTS : 1; /* [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */
638 volatile uint16_t CSCLR : 1; /* [13..13] Split Transaction CSPLIT Status Clear */
639 volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */
640 volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */
641 } DCPCTR_b;
642 };
643 volatile const uint16_t RESERVED10;
644
645 union {
646 volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */
647
648 struct TU_ATTR_PACKED {
649 volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
650 uint16_t : 12;
651 } PIPESEL_b;
652 };
653 volatile const uint16_t RESERVED11;
654
655 union {
656 volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */
657
658 struct TU_ATTR_PACKED {
659 volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */
660 volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */
661 uint16_t : 2;
662 volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
663 volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */
664 volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */
665 volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */
666 uint16_t : 3;
667 volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */
668 } PIPECFG_b;
669 };
670
671 union {
672 volatile uint16_t PIPEBUF;
674 struct {
675 volatile uint16_t BUFNMB : 8; // [7..0] Buffer NumberThese bits specify the FIFO buffer number of the selected pipe (04h to 87h)
676 uint16_t : 2;
677 volatile uint16_t BUFSIZE : 5;
678 uint16_t : 1;
679 } PIPEBUF_b;
680 };
681
682 union {
683 volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
684
685 struct TU_ATTR_PACKED {
686 volatile uint16_t MXPS : 11; /* [10..0] Maximum Packet Size */
687 uint16_t : 1;
688 volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
689 } PIPEMAXP_b;
690 };
691
692 union {
693 volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */
694
695 struct TU_ATTR_PACKED {
696 volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */
697 uint16_t : 9;
698 volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */
699 uint16_t : 3;
700 } PIPEPERI_b;
701 };
702
703 union {
704 volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */
705
706 struct TU_ATTR_PACKED {
707 volatile uint16_t PID : 2; /* [1..0] Response PID */
708 uint16_t : 3;
709 volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
710 volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */
711 volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */
712 volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */
713 volatile uint16_t ACLRM : 1; /* [9..9] Auto Buffer Clear Mode */
714 volatile uint16_t ATREPM : 1; /* [10..10] Auto Response Mode */
715 uint16_t : 1;
716 volatile const uint16_t CSSTS : 1; /* [12..12] CSSTS Status */
717 volatile uint16_t CSCLR : 1; /* [13..13] CSPLIT Status Clear */
718 volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */
719 volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */
720 } PIPE_CTR_b[9];
721 };
722 volatile const uint16_t RESERVED13;
723 volatile const uint32_t RESERVED14[3];
724 volatile RUSB2_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */
725 volatile const uint32_t RESERVED15[3];
726
727 union {
728 volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */
729
730 struct TU_ATTR_PACKED {
731 volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */
732 volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */
733 volatile uint16_t IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
734 volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
735 volatile uint16_t IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
736 volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
737 uint16_t : 1;
738 volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
739 volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */
740 volatile const uint16_t PDDETSTS0 : 1; /* [9..9] D+ Pin 0.6 V Input Detection Status */
741 uint16_t : 6;
742 } USBBCCTRL0_b;
743 };
744 volatile const uint16_t RESERVED16;
745 volatile const uint32_t RESERVED17[4];
746
747 union {
748 volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */
749
750 struct TU_ATTR_PACKED {
751 volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
752 uint16_t : 15;
753 } UCKSEL_b;
754 };
755 volatile const uint16_t RESERVED18;
756 volatile const uint32_t RESERVED19;
757
758 union {
759 volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */
760
761 struct TU_ATTR_PACKED {
762 volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */
763 uint16_t : 6;
764 volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */
765 uint16_t : 8;
766 } USBMC_b;
767 };
768 volatile const uint16_t RESERVED20;
769
770 union {
771 volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
772
773 struct TU_ATTR_PACKED {
774 uint16_t : 6;
775 volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */
776 volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
777 volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */
778 uint16_t : 1;
779 } DEVADD_b[10];
780 };
781 volatile const uint32_t RESERVED21[3];
782
783 union {
784 volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */
785
786 struct TU_ATTR_PACKED {
787 volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */
788 volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
789 volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
790 volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */
791 uint32_t : 28;
792 } PHYSLEW_b;
793 };
794 volatile const uint32_t RESERVED22[3];
795
796 union {
797 volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
798
799 struct TU_ATTR_PACKED {
800 uint16_t : 7;
801 volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
802 uint16_t : 8;
803 } LPCTRL_b;
804 };
805
806 union {
807 volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
808
809 struct TU_ATTR_PACKED {
810 uint16_t : 14;
811 volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
812 uint16_t : 1;
813 } LPSTS_b;
814 };
815 volatile const uint32_t RESERVED23[15];
816
817 union {
818 volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */
819
820 struct TU_ATTR_PACKED {
821 volatile uint16_t IDPSRCE : 1; /* [0..0] IDPSRC Control */
822 volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */
823 volatile uint16_t VDPSRCE : 1; /* [2..2] VDPSRC Control */
824 volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */
825 volatile uint16_t VDMSRCE : 1; /* [4..4] VDMSRC Control */
826 volatile uint16_t DCPMODE : 1; /* [5..5] DCP Mode Control */
827 uint16_t : 2;
828 volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
829 volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */
830 uint16_t : 6;
831 } BCCTRL_b;
832 };
833 volatile const uint16_t RESERVED24;
834
835 union {
836 volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */
837
838 struct TU_ATTR_PACKED {
839 volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */
840 volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */
841 volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */
842 volatile const uint16_t DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
843 volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */
844 uint16_t : 2;
845 volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */
846 uint16_t : 1;
847 } PL1CTRL1_b;
848 };
849
850 union {
851 volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
852
853 struct TU_ATTR_PACKED {
854 uint16_t : 8;
855 volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
856 volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */
857 uint16_t : 3;
858 } PL1CTRL2_b;
859 };
860
861 union {
862 volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */
863
864 struct TU_ATTR_PACKED {
865 volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */
866 volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
867 uint16_t : 13;
868 } HL1CTRL1_b;
869 };
870
871 union {
872 volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */
873
874 struct TU_ATTR_PACKED {
875 volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */
876 uint16_t : 4;
877 volatile uint16_t HIRD : 4; /* [11..8] LPM Token HIRD */
878 volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */
879 uint16_t : 2;
880 volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */
881 } HL1CTRL2_b;
882 };
883
884 volatile uint32_t RESERVED25_1;
885
886 union {
887 volatile uint16_t PHYTRIM1;
889 struct {
890 volatile uint16_t DRISE : 2;
891 volatile uint16_t DFALL : 2;
892 uint16_t : 3;
893 volatile uint16_t PCOMPENB : 1;
894 volatile uint16_t HSIUP : 4;
895 volatile uint16_t IMPOFFSET : 3;
896 uint16_t : 1;
897 } PHYTRIM1_b;
898 };
899
900 union {
901 volatile uint16_t PHYTRIM2;
903 struct {
904 volatile uint16_t SQU : 4;
905 uint16_t : 3;
906 volatile uint16_t HSRXENMO : 1;
907 volatile uint16_t PDR : 2;
908 uint16_t : 2;
909 volatile uint16_t DIS : 3;
910 uint16_t : 1;
911 } PHYTRIM2_b;
912 };
913 volatile uint32_t RESERVED25_2[3];
914
915 union {
916 volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
917
918 struct TU_ATTR_PACKED {
919 uint32_t : 20;
920 volatile const uint32_t DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
921 volatile const uint32_t DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
922 uint32_t : 1;
923 volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
924 uint32_t : 8;
925 } DPUSR0R_b;
926 };
927
928 union {
929 volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
930
931 struct TU_ATTR_PACKED {
932 uint32_t : 4;
933 volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
934 volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
935 uint32_t : 1;
936 volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */
937 uint32_t : 12;
938 volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */
939 volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
940 uint32_t : 1;
941 volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
942 uint32_t : 8;
943 } DPUSR1R_b;
944 };
945
946 union {
947 volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
948
949 struct TU_ATTR_PACKED {
950 volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */
951 volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */
952 uint16_t : 2;
953 volatile const uint16_t DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
954 volatile const uint16_t DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
955 uint16_t : 2;
956 volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */
957 volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */
958 uint16_t : 6;
959 } DPUSR2R_b;
960 };
961
962 union {
963 volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
964
965 struct TU_ATTR_PACKED {
966 volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */
967 volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
968 uint16_t : 14;
969 } DPUSRCR_b;
970 };
971 volatile const uint32_t RESERVED26[165];
972
973 union {
974 volatile uint32_t
975 DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */
976
977 struct TU_ATTR_PACKED {
978 volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */
979 volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */
980 uint32_t : 1;
981 volatile uint32_t DRPD0 : 1; /* [3..3] D+/D- Pull-Down Resistor Control */
982 volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */
983 uint32_t : 11;
984 volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
985 volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */
986 uint32_t : 2;
987 volatile const uint32_t DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
988 volatile const uint32_t DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
989 uint32_t : 1;
990 volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
991 uint32_t : 8;
992 } DPUSR0R_FS_b;
993 };
994
995 union {
996 volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */
997
998 struct TU_ATTR_PACKED {
999 volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */
1000 volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */
1001 uint32_t : 2;
1002 volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */
1003 volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */
1004 uint32_t : 1;
1005 volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */
1006 uint32_t : 8;
1007 volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */
1008 volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */
1009 uint32_t : 2;
1010 volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */
1011 volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
1012 uint32_t : 1;
1013 volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
1014 uint32_t : 8;
1015 } DPUSR1R_FS_b;
1016 };
1017} rusb2_reg_t; /* Size = 1032 (0x408) */
1018
1019TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
1020TU_ATTR_BIT_FIELD_ORDER_END
1021
1022/*--------------------------------------------------------------------*/
1023/* Register Bit Definitions */
1024/*--------------------------------------------------------------------*/
1025
1026// PIPE_TR
1027// E
1028#define RUSB2_PIPE_TR_E_TRENB_Pos (9UL) /* TRENB (Bit 9) */
1029#define RUSB2_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */
1030#define RUSB2_PIPE_TR_E_TRCLR_Pos (8UL) /* TRCLR (Bit 8) */
1031#define RUSB2_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */
1032
1033// N
1034#define RUSB2_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */
1035#define RUSB2_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */
1036
1037// Core Registers
1038
1039// SYSCFG
1040#define RUSB2_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */
1041#define RUSB2_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */
1042#define RUSB2_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */
1043#define RUSB2_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */
1044#define RUSB2_SYSCFG_HSE_Pos (7UL)
1045#define RUSB2_SYSCFG_HSE_Msk (0x80UL)
1046#define RUSB2_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */
1047#define RUSB2_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */
1048#define RUSB2_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */
1049#define RUSB2_SYSCFG_DRPD_Msk (0x20UL) /* DRPD (Bitfield-Mask: 0x01) */
1050#define RUSB2_SYSCFG_DPRPU_Pos (4UL) /* DPRPU (Bit 4) */
1051#define RUSB2_SYSCFG_DPRPU_Msk (0x10UL) /* DPRPU (Bitfield-Mask: 0x01) */
1052#define RUSB2_SYSCFG_DMRPU_Pos (3UL) /* DMRPU (Bit 3) */
1053#define RUSB2_SYSCFG_DMRPU_Msk (0x8UL) /* DMRPU (Bitfield-Mask: 0x01) */
1054#define RUSB2_SYSCFG_USBE_Pos (0UL) /* USBE (Bit 0) */
1055#define RUSB2_SYSCFG_USBE_Msk (0x1UL) /* USBE (Bitfield-Mask: 0x01) */
1056
1057// BUSWAIT
1058#define RUSB2_BUSWAIT_BWAIT_Pos (0UL) /* BWAIT (Bit 0) */
1059#define RUSB2_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */
1060
1061// SYSSTS0
1062#define RUSB2_SYSSTS0_OVCMON_Pos (14UL) /* OVCMON (Bit 14) */
1063#define RUSB2_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */
1064#define RUSB2_SYSSTS0_HTACT_Pos (6UL) /* HTACT (Bit 6) */
1065#define RUSB2_SYSSTS0_HTACT_Msk (0x40UL) /* HTACT (Bitfield-Mask: 0x01) */
1066#define RUSB2_SYSSTS0_SOFEA_Pos (5UL) /* SOFEA (Bit 5) */
1067#define RUSB2_SYSSTS0_SOFEA_Msk (0x20UL) /* SOFEA (Bitfield-Mask: 0x01) */
1068#define RUSB2_SYSSTS0_IDMON_Pos (2UL) /* IDMON (Bit 2) */
1069#define RUSB2_SYSSTS0_IDMON_Msk (0x4UL) /* IDMON (Bitfield-Mask: 0x01) */
1070#define RUSB2_SYSSTS0_LNST_Pos (0UL) /* LNST (Bit 0) */
1071#define RUSB2_SYSSTS0_LNST_Msk (0x3UL) /* LNST (Bitfield-Mask: 0x03) */
1072
1073// PLLSTA
1074#define RUSB2_PLLSTA_PLLLOCK_Pos (0UL) /* PLLLOCK (Bit 0) */
1075#define RUSB2_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */
1076
1077// DVSTCTR0
1078#define RUSB2_DVSTCTR0_HNPBTOA_Pos (11UL) /* HNPBTOA (Bit 11) */
1079#define RUSB2_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */
1080#define RUSB2_DVSTCTR0_EXICEN_Pos (10UL) /* EXICEN (Bit 10) */
1081#define RUSB2_DVSTCTR0_EXICEN_Msk (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */
1082#define RUSB2_DVSTCTR0_VBUSEN_Pos (9UL) /* VBUSEN (Bit 9) */
1083#define RUSB2_DVSTCTR0_VBUSEN_Msk (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */
1084#define RUSB2_DVSTCTR0_WKUP_Pos (8UL) /* WKUP (Bit 8) */
1085#define RUSB2_DVSTCTR0_WKUP_Msk (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */
1086#define RUSB2_DVSTCTR0_RWUPE_Pos (7UL) /* RWUPE (Bit 7) */
1087#define RUSB2_DVSTCTR0_RWUPE_Msk (0x80UL) /* RWUPE (Bitfield-Mask: 0x01) */
1088#define RUSB2_DVSTCTR0_USBRST_Pos (6UL) /* USBRST (Bit 6) */
1089#define RUSB2_DVSTCTR0_USBRST_Msk (0x40UL) /* USBRST (Bitfield-Mask: 0x01) */
1090#define RUSB2_DVSTCTR0_RESUME_Pos (5UL) /* RESUME (Bit 5) */
1091#define RUSB2_DVSTCTR0_RESUME_Msk (0x20UL) /* RESUME (Bitfield-Mask: 0x01) */
1092#define RUSB2_DVSTCTR0_UACT_Pos (4UL) /* UACT (Bit 4) */
1093#define RUSB2_DVSTCTR0_UACT_Msk (0x10UL) /* UACT (Bitfield-Mask: 0x01) */
1094#define RUSB2_DVSTCTR0_RHST_Pos (0UL) /* RHST (Bit 0) */
1095#define RUSB2_DVSTCTR0_RHST_Msk (0x7UL) /* RHST (Bitfield-Mask: 0x07) */
1096
1097// TESTMODE
1098#define RUSB2_TESTMODE_UTST_Pos (0UL) /* UTST (Bit 0) */
1099#define RUSB2_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */
1100
1101// CFIFOSEL
1102#define RUSB2_CFIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */
1103#define RUSB2_CFIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
1104#define RUSB2_CFIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */
1105#define RUSB2_CFIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */
1106#define RUSB2_CFIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */
1107#define RUSB2_CFIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */
1108#define RUSB2_CFIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */
1109#define RUSB2_CFIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */
1110#define RUSB2_CFIFOSEL_ISEL_Pos (5UL) /* ISEL (Bit 5) */
1111#define RUSB2_CFIFOSEL_ISEL_Msk (0x20UL) /* ISEL (Bitfield-Mask: 0x01) */
1112#define RUSB2_CFIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */
1113#define RUSB2_CFIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */
1114
1115// CFIFOCTR
1116#define RUSB2_CFIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */
1117#define RUSB2_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
1118#define RUSB2_CFIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */
1119#define RUSB2_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */
1120#define RUSB2_CFIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */
1121#define RUSB2_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
1122#define RUSB2_CFIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */
1123#define RUSB2_CFIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */
1124
1125// D0FIFOSEL
1126#define RUSB2_D0FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */
1127#define RUSB2_D0FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
1128#define RUSB2_D0FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */
1129#define RUSB2_D0FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */
1130#define RUSB2_D0FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */
1131#define RUSB2_D0FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */
1132#define RUSB2_D0FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */
1133#define RUSB2_D0FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */
1134#define RUSB2_D0FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */
1135#define RUSB2_D0FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */
1136#define RUSB2_D0FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */
1137#define RUSB2_D0FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */
1138#define RUSB2_D0FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */
1139#define RUSB2_D0FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */
1140
1141// D0FIFOCTR
1142#define RUSB2_D0FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */
1143#define RUSB2_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
1144#define RUSB2_D0FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */
1145#define RUSB2_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */
1146#define RUSB2_D0FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */
1147#define RUSB2_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
1148#define RUSB2_D0FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */
1149#define RUSB2_D0FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */
1150
1151// D1FIFOSEL
1152#define RUSB2_D1FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */
1153#define RUSB2_D1FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
1154#define RUSB2_D1FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */
1155#define RUSB2_D1FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */
1156#define RUSB2_D1FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */
1157#define RUSB2_D1FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */
1158#define RUSB2_D1FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */
1159#define RUSB2_D1FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */
1160#define RUSB2_D1FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */
1161#define RUSB2_D1FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */
1162#define RUSB2_D1FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */
1163#define RUSB2_D1FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */
1164#define RUSB2_D1FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */
1165#define RUSB2_D1FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */
1166
1167// D1FIFOCTR
1168#define RUSB2_D1FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */
1169#define RUSB2_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
1170#define RUSB2_D1FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */
1171#define RUSB2_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */
1172#define RUSB2_D1FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */
1173#define RUSB2_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
1174#define RUSB2_D1FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */
1175#define RUSB2_D1FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */
1176
1177// INTENB0
1178#define RUSB2_INTENB0_VBSE_Pos (15UL) /* VBSE (Bit 15) */
1179#define RUSB2_INTENB0_VBSE_Msk (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */
1180#define RUSB2_INTENB0_RSME_Pos (14UL) /* RSME (Bit 14) */
1181#define RUSB2_INTENB0_RSME_Msk (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */
1182#define RUSB2_INTENB0_SOFE_Pos (13UL) /* SOFE (Bit 13) */
1183#define RUSB2_INTENB0_SOFE_Msk (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */
1184#define RUSB2_INTENB0_DVSE_Pos (12UL) /* DVSE (Bit 12) */
1185#define RUSB2_INTENB0_DVSE_Msk (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */
1186#define RUSB2_INTENB0_CTRE_Pos (11UL) /* CTRE (Bit 11) */
1187#define RUSB2_INTENB0_CTRE_Msk (0x800UL) /* CTRE (Bitfield-Mask: 0x01) */
1188#define RUSB2_INTENB0_BEMPE_Pos (10UL) /* BEMPE (Bit 10) */
1189#define RUSB2_INTENB0_BEMPE_Msk (0x400UL) /* BEMPE (Bitfield-Mask: 0x01) */
1190#define RUSB2_INTENB0_NRDYE_Pos (9UL) /* NRDYE (Bit 9) */
1191#define RUSB2_INTENB0_NRDYE_Msk (0x200UL) /* NRDYE (Bitfield-Mask: 0x01) */
1192#define RUSB2_INTENB0_BRDYE_Pos (8UL) /* BRDYE (Bit 8) */
1193#define RUSB2_INTENB0_BRDYE_Msk (0x100UL) /* BRDYE (Bitfield-Mask: 0x01) */
1194
1195// INTENB1
1196#define RUSB2_INTENB1_OVRCRE_Pos (15UL) /* OVRCRE (Bit 15) */
1197#define RUSB2_INTENB1_OVRCRE_Msk (0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */
1198#define RUSB2_INTENB1_BCHGE_Pos (14UL) /* BCHGE (Bit 14) */
1199#define RUSB2_INTENB1_BCHGE_Msk (0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */
1200#define RUSB2_INTENB1_DTCHE_Pos (12UL) /* DTCHE (Bit 12) */
1201#define RUSB2_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */
1202#define RUSB2_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */
1203#define RUSB2_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */
1204#define RUSB2_INTENB1_L1RSMENDE_Pos (9UL)
1205#define RUSB2_INTENB1_L1RSMENDE_Msk (0x200UL)
1206#define RUSB2_INTENB1_LPMENDE_Pos (8UL)
1207#define RUSB2_INTENB1_LPMENDE_Msk (0x100UL)
1208#define RUSB2_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */
1209#define RUSB2_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */
1210#define RUSB2_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */
1211#define RUSB2_INTENB1_SIGNE_Msk (0x20UL) /* SIGNE (Bitfield-Mask: 0x01) */
1212#define RUSB2_INTENB1_SACKE_Pos (4UL) /* SACKE (Bit 4) */
1213#define RUSB2_INTENB1_SACKE_Msk (0x10UL) /* SACKE (Bitfield-Mask: 0x01) */
1214#define RUSB2_INTENB1_PDDETINTE0_Pos (0UL) /* PDDETINTE0 (Bit 0) */
1215#define RUSB2_INTENB1_PDDETINTE0_Msk (0x1UL) /* PDDETINTE0 (Bitfield-Mask: 0x01) */
1216
1217// BRDYENB
1218#define RUSB2_BRDYENB_PIPEBRDYE_Pos (0UL) /* PIPEBRDYE (Bit 0) */
1219#define RUSB2_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */
1220
1221// NRDYENB
1222#define RUSB2_NRDYENB_PIPENRDYE_Pos (0UL) /* PIPENRDYE (Bit 0) */
1223#define RUSB2_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */
1224
1225// BEMPENB
1226#define RUSB2_BEMPENB_PIPEBEMPE_Pos (0UL) /* PIPEBEMPE (Bit 0) */
1227#define RUSB2_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */
1228
1229// SOFCFG
1230#define RUSB2_SOFCFG_TRNENSEL_Pos (8UL) /* TRNENSEL (Bit 8) */
1231#define RUSB2_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */
1232#define RUSB2_SOFCFG_BRDYM_Pos (6UL) /* BRDYM (Bit 6) */
1233#define RUSB2_SOFCFG_BRDYM_Msk (0x40UL) /* BRDYM (Bitfield-Mask: 0x01) */
1234#define RUSB2_SOFCFG_INTL_Pos (5UL) /* INTL (Bit 5) */
1235#define RUSB2_SOFCFG_INTL_Msk (0x20UL) /* INTL (Bitfield-Mask: 0x01) */
1236#define RUSB2_SOFCFG_EDGESTS_Pos (4UL) /* EDGESTS (Bit 4) */
1237#define RUSB2_SOFCFG_EDGESTS_Msk (0x10UL) /* EDGESTS (Bitfield-Mask: 0x01) */
1238
1239// PHYSET
1240#define RUSB2_PHYSET_HSEB_Pos (15UL) /* HSEB (Bit 15) */
1241#define RUSB2_PHYSET_HSEB_Msk (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */
1242#define RUSB2_PHYSET_REPSTART_Pos (11UL) /* REPSTART (Bit 11) */
1243#define RUSB2_PHYSET_REPSTART_Msk (0x800UL) /* REPSTART (Bitfield-Mask: 0x01) */
1244#define RUSB2_PHYSET_REPSEL_Pos (8UL) /* REPSEL (Bit 8) */
1245#define RUSB2_PHYSET_REPSEL_Msk (0x300UL) /* REPSEL (Bitfield-Mask: 0x03) */
1246#define RUSB2_PHYSET_CLKSEL_Pos (4UL) /* CLKSEL (Bit 4) */
1247#define RUSB2_PHYSET_CLKSEL_Msk (0x30UL) /* CLKSEL (Bitfield-Mask: 0x03) */
1248#define RUSB2_PHYSET_CDPEN_Pos (3UL) /* CDPEN (Bit 3) */
1249#define RUSB2_PHYSET_CDPEN_Msk (0x8UL) /* CDPEN (Bitfield-Mask: 0x01) */
1250#define RUSB2_PHYSET_PLLRESET_Pos (1UL) /* PLLRESET (Bit 1) */
1251#define RUSB2_PHYSET_PLLRESET_Msk (0x2UL) /* PLLRESET (Bitfield-Mask: 0x01) */
1252#define RUSB2_PHYSET_DIRPD_Pos (0UL) /* DIRPD (Bit 0) */
1253#define RUSB2_PHYSET_DIRPD_Msk (0x1UL) /* DIRPD (Bitfield-Mask: 0x01) */
1254
1255// INTSTS0
1256#define RUSB2_INTSTS0_VBINT_Pos (15UL) /* VBINT (Bit 15) */
1257#define RUSB2_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */
1258#define RUSB2_INTSTS0_RESM_Pos (14UL) /* RESM (Bit 14) */
1259#define RUSB2_INTSTS0_RESM_Msk (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */
1260#define RUSB2_INTSTS0_SOFR_Pos (13UL) /* SOFR (Bit 13) */
1261#define RUSB2_INTSTS0_SOFR_Msk (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */
1262#define RUSB2_INTSTS0_DVST_Pos (12UL) /* DVST (Bit 12) */
1263#define RUSB2_INTSTS0_DVST_Msk (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */
1264#define RUSB2_INTSTS0_CTRT_Pos (11UL) /* CTRT (Bit 11) */
1265#define RUSB2_INTSTS0_CTRT_Msk (0x800UL) /* CTRT (Bitfield-Mask: 0x01) */
1266#define RUSB2_INTSTS0_BEMP_Pos (10UL) /* BEMP (Bit 10) */
1267#define RUSB2_INTSTS0_BEMP_Msk (0x400UL) /* BEMP (Bitfield-Mask: 0x01) */
1268#define RUSB2_INTSTS0_NRDY_Pos (9UL) /* NRDY (Bit 9) */
1269#define RUSB2_INTSTS0_NRDY_Msk (0x200UL) /* NRDY (Bitfield-Mask: 0x01) */
1270#define RUSB2_INTSTS0_BRDY_Pos (8UL) /* BRDY (Bit 8) */
1271#define RUSB2_INTSTS0_BRDY_Msk (0x100UL) /* BRDY (Bitfield-Mask: 0x01) */
1272#define RUSB2_INTSTS0_VBSTS_Pos (7UL) /* VBSTS (Bit 7) */
1273#define RUSB2_INTSTS0_VBSTS_Msk (0x80UL) /* VBSTS (Bitfield-Mask: 0x01) */
1274#define RUSB2_INTSTS0_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */
1275#define RUSB2_INTSTS0_DVSQ_Msk (0x70UL) /* DVSQ (Bitfield-Mask: 0x07) */
1276#define RUSB2_INTSTS0_VALID_Pos (3UL) /* VALID (Bit 3) */
1277#define RUSB2_INTSTS0_VALID_Msk (0x8UL) /* VALID (Bitfield-Mask: 0x01) */
1278#define RUSB2_INTSTS0_CTSQ_Pos (0UL) /* CTSQ (Bit 0) */
1279#define RUSB2_INTSTS0_CTSQ_Msk (0x7UL) /* CTSQ (Bitfield-Mask: 0x07) */
1280
1281// INTSTS1
1282#define RUSB2_INTSTS1_OVRCR_Pos (15UL) /* OVRCR (Bit 15) */
1283#define RUSB2_INTSTS1_OVRCR_Msk (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */
1284#define RUSB2_INTSTS1_BCHG_Pos (14UL) /* BCHG (Bit 14) */
1285#define RUSB2_INTSTS1_BCHG_Msk (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */
1286#define RUSB2_INTSTS1_DTCH_Pos (12UL) /* DTCH (Bit 12) */
1287#define RUSB2_INTSTS1_DTCH_Msk (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */
1288#define RUSB2_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */
1289#define RUSB2_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */
1290#define RUSB2_INTSTS1_L1RSMEND_Pos (9UL) /* L1RSMEND (Bit 9) */
1291#define RUSB2_INTSTS1_L1RSMEND_Msk (0x200UL) /* L1RSMEND (Bitfield-Mask: 0x01) */
1292#define RUSB2_INTSTS1_LPMEND_Pos (8UL) /* LPMEND (Bit 8) */
1293#define RUSB2_INTSTS1_LPMEND_Msk (0x100UL) /* LPMEND (Bitfield-Mask: 0x01) */
1294#define RUSB2_INTSTS1_EOFERR_Pos (6UL) /* EOFERR (Bit 6) */
1295#define RUSB2_INTSTS1_EOFERR_Msk (0x40UL) /* EOFERR (Bitfield-Mask: 0x01) */
1296#define RUSB2_INTSTS1_SIGN_Pos (5UL) /* SIGN (Bit 5) */
1297#define RUSB2_INTSTS1_SIGN_Msk (0x20UL) /* SIGN (Bitfield-Mask: 0x01) */
1298#define RUSB2_INTSTS1_SACK_Pos (4UL) /* SACK (Bit 4) */
1299#define RUSB2_INTSTS1_SACK_Msk (0x10UL) /* SACK (Bitfield-Mask: 0x01) */
1300#define RUSB2_INTSTS1_PDDETINT0_Pos (0UL) /* PDDETINT0 (Bit 0) */
1301#define RUSB2_INTSTS1_PDDETINT0_Msk (0x1UL) /* PDDETINT0 (Bitfield-Mask: 0x01) */
1302
1303// BRDYSTS
1304#define RUSB2_BRDYSTS_PIPEBRDY_Pos (0UL) /* PIPEBRDY (Bit 0) */
1305#define RUSB2_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */
1306
1307// NRDYSTS
1308#define RUSB2_NRDYSTS_PIPENRDY_Pos (0UL) /* PIPENRDY (Bit 0) */
1309#define RUSB2_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */
1310
1311// BEMPSTS
1312#define RUSB2_BEMPSTS_PIPEBEMP_Pos (0UL) /* PIPEBEMP (Bit 0) */
1313#define RUSB2_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */
1314
1315// FRMNUM
1316#define RUSB2_FRMNUM_OVRN_Pos (15UL) /* OVRN (Bit 15) */
1317#define RUSB2_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */
1318#define RUSB2_FRMNUM_CRCE_Pos (14UL) /* CRCE (Bit 14) */
1319#define RUSB2_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */
1320#define RUSB2_FRMNUM_FRNM_Pos (0UL) /* FRNM (Bit 0) */
1321#define RUSB2_FRMNUM_FRNM_Msk (0x7ffUL) /* FRNM (Bitfield-Mask: 0x7ff) */
1322
1323// UFRMNUM
1324#define RUSB2_UFRMNUM_DVCHG_Pos (15UL) /* DVCHG (Bit 15) */
1325#define RUSB2_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */
1326#define RUSB2_UFRMNUM_UFRNM_Pos (0UL) /* UFRNM (Bit 0) */
1327#define RUSB2_UFRMNUM_UFRNM_Msk (0x7UL) /* UFRNM (Bitfield-Mask: 0x07) */
1328
1329// USBADDR
1330#define RUSB2_USBADDR_STSRECOV0_Pos (8UL) /* STSRECOV0 (Bit 8) */
1331#define RUSB2_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */
1332#define RUSB2_USBADDR_USBADDR_Pos (0UL) /* USBADDR (Bit 0) */
1333#define RUSB2_USBADDR_USBADDR_Msk (0x7fUL) /* USBADDR (Bitfield-Mask: 0x7f) */
1334
1335// USBREQ
1336#define RUSB2_USBREQ_BREQUEST_Pos (8UL) /* BREQUEST (Bit 8) */
1337#define RUSB2_USBREQ_BREQUEST_Msk (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */
1338#define RUSB2_USBREQ_BMREQUESTTYPE_Pos (0UL) /* BMREQUESTTYPE (Bit 0) */
1339#define RUSB2_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */
1340
1341// USBVAL
1342#define RUSB2_USBVAL_WVALUE_Pos (0UL) /* WVALUE (Bit 0) */
1343#define RUSB2_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */
1344
1345// USBINDX
1346#define RUSB2_USBINDX_WINDEX_Pos (0UL) /* WINDEX (Bit 0) */
1347#define RUSB2_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */
1348
1349// USBLENG
1350#define RUSB2_USBLENG_WLENGTH_Pos (0UL) /* WLENGTH (Bit 0) */
1351#define RUSB2_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */
1352
1353// DCPCFG
1354#define RUSB2_DCPCFG_CNTMD_Pos (8UL) /* CNTMD (Bit 8) */
1355#define RUSB2_DCPCFG_CNTMD_Msk (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */
1356#define RUSB2_DCPCFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */
1357#define RUSB2_DCPCFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */
1358#define RUSB2_DCPCFG_DIR_Pos (4UL) /* DIR (Bit 4) */
1359#define RUSB2_DCPCFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */
1360
1361// DCPMAXP
1362#define RUSB2_DCPMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */
1363#define RUSB2_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */
1364#define RUSB2_DCPMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */
1365#define RUSB2_DCPMAXP_MXPS_Msk (0x7fUL) /* MXPS (Bitfield-Mask: 0x7f) */
1366
1367// DCPCTR
1368#define RUSB2_DCPCTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */
1369#define RUSB2_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */
1370#define RUSB2_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */
1371#define RUSB2_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */
1372#define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL)
1373#define RUSB2_DCPCTR_CSCLR_Msk (0x2000UL)
1374#define RUSB2_DCPCTR_CSSTS_Pos (12UL)
1375#define RUSB2_DCPCTR_CSSTS_Msk (0x1000UL)
1376#define RUSB2_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */
1377#define RUSB2_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */
1378#define RUSB2_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */
1379#define RUSB2_DCPCTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */
1380#define RUSB2_DCPCTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */
1381#define RUSB2_DCPCTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */
1382#define RUSB2_DCPCTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */
1383#define RUSB2_DCPCTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */
1384#define RUSB2_DCPCTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */
1385#define RUSB2_DCPCTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */
1386#define RUSB2_DCPCTR_CCPL_Pos (2UL) /* CCPL (Bit 2) */
1387#define RUSB2_DCPCTR_CCPL_Msk (0x4UL) /* CCPL (Bitfield-Mask: 0x01) */
1388#define RUSB2_DCPCTR_PID_Pos (0UL) /* PID (Bit 0) */
1389#define RUSB2_DCPCTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */
1390
1391// PIPESEL
1392#define RUSB2_PIPESEL_PIPESEL_Pos (0UL) /* PIPESEL (Bit 0) */
1393#define RUSB2_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */
1394
1395// PIPECFG
1396#define RUSB2_PIPECFG_TYPE_Pos (14UL) /* TYPE (Bit 14) */
1397#define RUSB2_PIPECFG_TYPE_Msk (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */
1398#define RUSB2_PIPECFG_BFRE_Pos (10UL) /* BFRE (Bit 10) */
1399#define RUSB2_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */
1400#define RUSB2_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */
1401#define RUSB2_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */
1402#define RUSB2_PIPECFG_CNTMD_Pos (8UL)
1403#define RUSB2_PIPECFG_CNTMD_Msk (0x100UL)
1404#define RUSB2_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */
1405#define RUSB2_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */
1406#define RUSB2_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */
1407#define RUSB2_PIPECFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */
1408#define RUSB2_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */
1409#define RUSB2_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */
1410
1411// PIPEBUF
1412#define RUSB2_PIPEBUF_BUFSIZE_Pos (10UL)
1413#define RUSB2_PIPEBUF_BUFSIZE_Msk (0x7c00UL)
1414#define RUSB2_PIPEBUF_BUFNMB_Pos (0UL)
1415#define RUSB2_PIPEBUF_BUFNMB_Msk (0xffUL)
1417// PIPEMAXP
1418#define RUSB2_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */
1419#define RUSB2_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */
1420#define RUSB2_PIPEMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */
1421#define RUSB2_PIPEMAXP_MXPS_Msk (0x1ffUL) /* MXPS (Bitfield-Mask: 0x1ff) */
1422
1423// PIPEPERI
1424#define RUSB2_PIPEPERI_IFIS_Pos (12UL) /* IFIS (Bit 12) */
1425#define RUSB2_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */
1426#define RUSB2_PIPEPERI_IITV_Pos (0UL) /* IITV (Bit 0) */
1427#define RUSB2_PIPEPERI_IITV_Msk (0x7UL) /* IITV (Bitfield-Mask: 0x07) */
1428
1429// PIPE_CTR
1430#define RUSB2_PIPE_CTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */
1431#define RUSB2_PIPE_CTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */
1432#define RUSB2_PIPE_CTR_INBUFM_Pos (14UL) /* INBUFM (Bit 14) */
1433#define RUSB2_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */
1434#define RUSB2_PIPE_CTR_CSCLR_Pos (13UL) /* CSCLR (Bit 13) */
1435#define RUSB2_PIPE_CTR_CSCLR_Msk (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */
1436#define RUSB2_PIPE_CTR_CSSTS_Pos (12UL) /* CSSTS (Bit 12) */
1437#define RUSB2_PIPE_CTR_CSSTS_Msk (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */
1438#define RUSB2_PIPE_CTR_ATREPM_Pos (10UL) /* ATREPM (Bit 10) */
1439#define RUSB2_PIPE_CTR_ATREPM_Msk (0x400UL) /* ATREPM (Bitfield-Mask: 0x01) */
1440#define RUSB2_PIPE_CTR_ACLRM_Pos (9UL) /* ACLRM (Bit 9) */
1441#define RUSB2_PIPE_CTR_ACLRM_Msk (0x200UL) /* ACLRM (Bitfield-Mask: 0x01) */
1442#define RUSB2_PIPE_CTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */
1443#define RUSB2_PIPE_CTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */
1444#define RUSB2_PIPE_CTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */
1445#define RUSB2_PIPE_CTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */
1446#define RUSB2_PIPE_CTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */
1447#define RUSB2_PIPE_CTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */
1448#define RUSB2_PIPE_CTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */
1449#define RUSB2_PIPE_CTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */
1450#define RUSB2_PIPE_CTR_PID_Pos (0UL) /* PID (Bit 0) */
1451#define RUSB2_PIPE_CTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */
1452
1453// DEVADD
1454#define RUSB2_DEVADD_UPPHUB_Pos (11UL) /* UPPHUB (Bit 11) */
1455#define RUSB2_DEVADD_UPPHUB_Msk (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */
1456#define RUSB2_DEVADD_HUBPORT_Pos (8UL) /* HUBPORT (Bit 8) */
1457#define RUSB2_DEVADD_HUBPORT_Msk (0x700UL) /* HUBPORT (Bitfield-Mask: 0x07) */
1458#define RUSB2_DEVADD_USBSPD_Pos (6UL) /* USBSPD (Bit 6) */
1459#define RUSB2_DEVADD_USBSPD_Msk (0xc0UL) /* USBSPD (Bitfield-Mask: 0x03) */
1460
1461// USBBCCTRL0
1462#define RUSB2_USBBCCTRL0_PDDETSTS0_Pos (9UL) /* PDDETSTS0 (Bit 9) */
1463#define RUSB2_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */
1464#define RUSB2_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /* CHGDETSTS0 (Bit 8) */
1465#define RUSB2_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */
1466#define RUSB2_USBBCCTRL0_BATCHGE0_Pos (7UL) /* BATCHGE0 (Bit 7) */
1467#define RUSB2_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /* BATCHGE0 (Bitfield-Mask: 0x01) */
1468#define RUSB2_USBBCCTRL0_VDMSRCE0_Pos (5UL) /* VDMSRCE0 (Bit 5) */
1469#define RUSB2_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /* VDMSRCE0 (Bitfield-Mask: 0x01) */
1470#define RUSB2_USBBCCTRL0_IDPSINKE0_Pos (4UL) /* IDPSINKE0 (Bit 4) */
1471#define RUSB2_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /* IDPSINKE0 (Bitfield-Mask: 0x01) */
1472#define RUSB2_USBBCCTRL0_VDPSRCE0_Pos (3UL) /* VDPSRCE0 (Bit 3) */
1473#define RUSB2_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /* VDPSRCE0 (Bitfield-Mask: 0x01) */
1474#define RUSB2_USBBCCTRL0_IDMSINKE0_Pos (2UL) /* IDMSINKE0 (Bit 2) */
1475#define RUSB2_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /* IDMSINKE0 (Bitfield-Mask: 0x01) */
1476#define RUSB2_USBBCCTRL0_IDPSRCE0_Pos (1UL) /* IDPSRCE0 (Bit 1) */
1477#define RUSB2_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /* IDPSRCE0 (Bitfield-Mask: 0x01) */
1478#define RUSB2_USBBCCTRL0_RPDME0_Pos (0UL) /* RPDME0 (Bit 0) */
1479#define RUSB2_USBBCCTRL0_RPDME0_Msk (0x1UL) /* RPDME0 (Bitfield-Mask: 0x01) */
1480
1481// UCKSEL
1482#define RUSB2_UCKSEL_UCKSELC_Pos (0UL) /* UCKSELC (Bit 0) */
1483#define RUSB2_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */
1484
1485// USBMC
1486#define RUSB2_USBMC_VDCEN_Pos (7UL) /* VDCEN (Bit 7) */
1487#define RUSB2_USBMC_VDCEN_Msk (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */
1488#define RUSB2_USBMC_VDDUSBE_Pos (0UL) /* VDDUSBE (Bit 0) */
1489#define RUSB2_USBMC_VDDUSBE_Msk (0x1UL) /* VDDUSBE (Bitfield-Mask: 0x01) */
1490
1491// PHYSLEW
1492#define RUSB2_PHYSLEW_SLEWF01_Pos (3UL) /* SLEWF01 (Bit 3) */
1493#define RUSB2_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */
1494#define RUSB2_PHYSLEW_SLEWF00_Pos (2UL) /* SLEWF00 (Bit 2) */
1495#define RUSB2_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */
1496#define RUSB2_PHYSLEW_SLEWR01_Pos (1UL) /* SLEWR01 (Bit 1) */
1497#define RUSB2_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */
1498#define RUSB2_PHYSLEW_SLEWR00_Pos (0UL) /* SLEWR00 (Bit 0) */
1499#define RUSB2_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */
1500
1501// LPCTRL
1502#define RUSB2_LPCTRL_HWUPM_Pos (7UL) /* HWUPM (Bit 7) */
1503#define RUSB2_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */
1504
1505// LPSTS
1506#define RUSB2_LPSTS_SUSPENDM_Pos (14UL) /* SUSPENDM (Bit 14) */
1507#define RUSB2_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */
1508
1509// BCCTRL
1510#define RUSB2_BCCTRL_PDDETSTS_Pos (9UL) /* PDDETSTS (Bit 9) */
1511#define RUSB2_BCCTRL_PDDETSTS_Msk (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */
1512#define RUSB2_BCCTRL_CHGDETSTS_Pos (8UL) /* CHGDETSTS (Bit 8) */
1513#define RUSB2_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */
1514#define RUSB2_BCCTRL_DCPMODE_Pos (5UL) /* DCPMODE (Bit 5) */
1515#define RUSB2_BCCTRL_DCPMODE_Msk (0x20UL) /* DCPMODE (Bitfield-Mask: 0x01) */
1516#define RUSB2_BCCTRL_VDMSRCE_Pos (4UL) /* VDMSRCE (Bit 4) */
1517#define RUSB2_BCCTRL_VDMSRCE_Msk (0x10UL) /* VDMSRCE (Bitfield-Mask: 0x01) */
1518#define RUSB2_BCCTRL_IDPSINKE_Pos (3UL) /* IDPSINKE (Bit 3) */
1519#define RUSB2_BCCTRL_IDPSINKE_Msk (0x8UL) /* IDPSINKE (Bitfield-Mask: 0x01) */
1520#define RUSB2_BCCTRL_VDPSRCE_Pos (2UL) /* VDPSRCE (Bit 2) */
1521#define RUSB2_BCCTRL_VDPSRCE_Msk (0x4UL) /* VDPSRCE (Bitfield-Mask: 0x01) */
1522#define RUSB2_BCCTRL_IDMSINKE_Pos (1UL) /* IDMSINKE (Bit 1) */
1523#define RUSB2_BCCTRL_IDMSINKE_Msk (0x2UL) /* IDMSINKE (Bitfield-Mask: 0x01) */
1524#define RUSB2_BCCTRL_IDPSRCE_Pos (0UL) /* IDPSRCE (Bit 0) */
1525#define RUSB2_BCCTRL_IDPSRCE_Msk (0x1UL) /* IDPSRCE (Bitfield-Mask: 0x01) */
1526
1527// PL1CTRL1
1528#define RUSB2_PL1CTRL1_L1EXTMD_Pos (14UL) /* L1EXTMD (Bit 14) */
1529#define RUSB2_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */
1530#define RUSB2_PL1CTRL1_HIRDTHR_Pos (8UL) /* HIRDTHR (Bit 8) */
1531#define RUSB2_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /* HIRDTHR (Bitfield-Mask: 0x0f) */
1532#define RUSB2_PL1CTRL1_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */
1533#define RUSB2_PL1CTRL1_DVSQ_Msk (0xf0UL) /* DVSQ (Bitfield-Mask: 0x0f) */
1534#define RUSB2_PL1CTRL1_L1NEGOMD_Pos (3UL) /* L1NEGOMD (Bit 3) */
1535#define RUSB2_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /* L1NEGOMD (Bitfield-Mask: 0x01) */
1536#define RUSB2_PL1CTRL1_L1RESPMD_Pos (1UL) /* L1RESPMD (Bit 1) */
1537#define RUSB2_PL1CTRL1_L1RESPMD_Msk (0x6UL) /* L1RESPMD (Bitfield-Mask: 0x03) */
1538#define RUSB2_PL1CTRL1_L1RESPEN_Pos (0UL) /* L1RESPEN (Bit 0) */
1539#define RUSB2_PL1CTRL1_L1RESPEN_Msk (0x1UL) /* L1RESPEN (Bitfield-Mask: 0x01) */
1540
1541// PL1CTRL2
1542#define RUSB2_PL1CTRL2_RWEMON_Pos (12UL) /* RWEMON (Bit 12) */
1543#define RUSB2_PL1CTRL2_RWEMON_Msk (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */
1544#define RUSB2_PL1CTRL2_HIRDMON_Pos (8UL) /* HIRDMON (Bit 8) */
1545#define RUSB2_PL1CTRL2_HIRDMON_Msk (0xf00UL) /* HIRDMON (Bitfield-Mask: 0x0f) */
1546
1547// HL1CTRL1
1548#define RUSB2_HL1CTRL1_L1STATUS_Pos (1UL) /* L1STATUS (Bit 1) */
1549#define RUSB2_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */
1550#define RUSB2_HL1CTRL1_L1REQ_Pos (0UL) /* L1REQ (Bit 0) */
1551#define RUSB2_HL1CTRL1_L1REQ_Msk (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */
1552
1553// HL1CTRL2
1554#define RUSB2_HL1CTRL2_BESL_Pos (15UL) /* BESL (Bit 15) */
1555#define RUSB2_HL1CTRL2_BESL_Msk (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */
1556#define RUSB2_HL1CTRL2_L1RWE_Pos (12UL) /* L1RWE (Bit 12) */
1557#define RUSB2_HL1CTRL2_L1RWE_Msk (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */
1558#define RUSB2_HL1CTRL2_HIRD_Pos (8UL) /* HIRD (Bit 8) */
1559#define RUSB2_HL1CTRL2_HIRD_Msk (0xf00UL) /* HIRD (Bitfield-Mask: 0x0f) */
1560#define RUSB2_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */
1561#define RUSB2_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */
1562
1563// PHYTRIM1
1564#define RUSB2_PHYTRIM1_IMPOFFSET_Pos (12UL)
1565#define RUSB2_PHYTRIM1_IMPOFFSET_Msk (0x7000UL)
1566#define RUSB2_PHYTRIM1_HSIUP_Pos (8UL)
1567#define RUSB2_PHYTRIM1_HSIUP_Msk (0xf00UL)
1568#define RUSB2_PHYTRIM1_PCOMPENB_Pos (7UL)
1569#define RUSB2_PHYTRIM1_PCOMPENB_Msk (0x80UL)
1570#define RUSB2_PHYTRIM1_DFALL_Pos (2UL)
1571#define RUSB2_PHYTRIM1_DFALL_Msk (0xcUL)
1572#define RUSB2_PHYTRIM1_DRISE_Pos (0UL)
1573#define RUSB2_PHYTRIM1_DRISE_Msk (0x3UL)
1575// PHYTRIM2
1576#define RUSB2_PHYTRIM2_DIS_Pos (12UL)
1577#define RUSB2_PHYTRIM2_DIS_Msk (0x7000UL)
1578#define RUSB2_PHYTRIM2_PDR_Pos (8UL)
1579#define RUSB2_PHYTRIM2_PDR_Msk (0x300UL)
1580#define RUSB2_PHYTRIM2_HSRXENMO_Pos (7UL)
1581#define RUSB2_PHYTRIM2_HSRXENMO_Msk (0x80UL)
1582#define RUSB2_PHYTRIM2_SQU_Pos (0UL)
1583#define RUSB2_PHYTRIM2_SQU_Msk (0xfUL)
1585// DPUSR0R
1586#define RUSB2_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */
1587#define RUSB2_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
1588#define RUSB2_DPUSR0R_DOVCBHM_Pos (21UL) /* DOVCBHM (Bit 21) */
1589#define RUSB2_DPUSR0R_DOVCBHM_Msk (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */
1590#define RUSB2_DPUSR0R_DOVCAHM_Pos (20UL) /* DOVCAHM (Bit 20) */
1591#define RUSB2_DPUSR0R_DOVCAHM_Msk (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */
1592
1593// DPUSR1R
1594#define RUSB2_DPUSR1R_DVBSTSH_Pos (23UL) /* DVBSTSH (Bit 23) */
1595#define RUSB2_DPUSR1R_DVBSTSH_Msk (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */
1596#define RUSB2_DPUSR1R_DOVCBH_Pos (21UL) /* DOVCBH (Bit 21) */
1597#define RUSB2_DPUSR1R_DOVCBH_Msk (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */
1598#define RUSB2_DPUSR1R_DOVCAH_Pos (20UL) /* DOVCAH (Bit 20) */
1599#define RUSB2_DPUSR1R_DOVCAH_Msk (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */
1600#define RUSB2_DPUSR1R_DVBSTSHE_Pos (7UL) /* DVBSTSHE (Bit 7) */
1601#define RUSB2_DPUSR1R_DVBSTSHE_Msk (0x80UL) /* DVBSTSHE (Bitfield-Mask: 0x01) */
1602#define RUSB2_DPUSR1R_DOVCBHE_Pos (5UL) /* DOVCBHE (Bit 5) */
1603#define RUSB2_DPUSR1R_DOVCBHE_Msk (0x20UL) /* DOVCBHE (Bitfield-Mask: 0x01) */
1604#define RUSB2_DPUSR1R_DOVCAHE_Pos (4UL) /* DOVCAHE (Bit 4) */
1605#define RUSB2_DPUSR1R_DOVCAHE_Msk (0x10UL) /* DOVCAHE (Bitfield-Mask: 0x01) */
1606
1607// DPUSR2R
1608#define RUSB2_DPUSR2R_DMINTE_Pos (9UL) /* DMINTE (Bit 9) */
1609#define RUSB2_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */
1610#define RUSB2_DPUSR2R_DPINTE_Pos (8UL) /* DPINTE (Bit 8) */
1611#define RUSB2_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */
1612#define RUSB2_DPUSR2R_DMVAL_Pos (5UL) /* DMVAL (Bit 5) */
1613#define RUSB2_DPUSR2R_DMVAL_Msk (0x20UL) /* DMVAL (Bitfield-Mask: 0x01) */
1614#define RUSB2_DPUSR2R_DPVAL_Pos (4UL) /* DPVAL (Bit 4) */
1615#define RUSB2_DPUSR2R_DPVAL_Msk (0x10UL) /* DPVAL (Bitfield-Mask: 0x01) */
1616#define RUSB2_DPUSR2R_DMINT_Pos (1UL) /* DMINT (Bit 1) */
1617#define RUSB2_DPUSR2R_DMINT_Msk (0x2UL) /* DMINT (Bitfield-Mask: 0x01) */
1618#define RUSB2_DPUSR2R_DPINT_Pos (0UL) /* DPINT (Bit 0) */
1619#define RUSB2_DPUSR2R_DPINT_Msk (0x1UL) /* DPINT (Bitfield-Mask: 0x01) */
1620
1621// DPUSRCR
1622#define RUSB2_DPUSRCR_FIXPHYPD_Pos (1UL) /* FIXPHYPD (Bit 1) */
1623#define RUSB2_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */
1624#define RUSB2_DPUSRCR_FIXPHY_Pos (0UL) /* FIXPHY (Bit 0) */
1625#define RUSB2_DPUSRCR_FIXPHY_Msk (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */
1626
1627// DPUSR0R_FS
1628#define RUSB2_DPUSR0R_FS_DVBSTS0_Pos (23UL) /* DVBSTS0 (Bit 23) */
1629#define RUSB2_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */
1630#define RUSB2_DPUSR0R_FS_DOVCB0_Pos (21UL) /* DOVCB0 (Bit 21) */
1631#define RUSB2_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */
1632#define RUSB2_DPUSR0R_FS_DOVCA0_Pos (20UL) /* DOVCA0 (Bit 20) */
1633#define RUSB2_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */
1634#define RUSB2_DPUSR0R_FS_DM0_Pos (17UL) /* DM0 (Bit 17) */
1635#define RUSB2_DPUSR0R_FS_DM0_Msk (0x20000UL) /* DM0 (Bitfield-Mask: 0x01) */
1636#define RUSB2_DPUSR0R_FS_DP0_Pos (16UL) /* DP0 (Bit 16) */
1637#define RUSB2_DPUSR0R_FS_DP0_Msk (0x10000UL) /* DP0 (Bitfield-Mask: 0x01) */
1638#define RUSB2_DPUSR0R_FS_FIXPHY0_Pos (4UL) /* FIXPHY0 (Bit 4) */
1639#define RUSB2_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /* FIXPHY0 (Bitfield-Mask: 0x01) */
1640#define RUSB2_DPUSR0R_FS_DRPD0_Pos (3UL) /* DRPD0 (Bit 3) */
1641#define RUSB2_DPUSR0R_FS_DRPD0_Msk (0x8UL) /* DRPD0 (Bitfield-Mask: 0x01) */
1642#define RUSB2_DPUSR0R_FS_RPUE0_Pos (1UL) /* RPUE0 (Bit 1) */
1643#define RUSB2_DPUSR0R_FS_RPUE0_Msk (0x2UL) /* RPUE0 (Bitfield-Mask: 0x01) */
1644#define RUSB2_DPUSR0R_FS_SRPC0_Pos (0UL) /* SRPC0 (Bit 0) */
1645#define RUSB2_DPUSR0R_FS_SRPC0_Msk (0x1UL) /* SRPC0 (Bitfield-Mask: 0x01) */
1646
1647// DPUSR1R_FS
1648#define RUSB2_DPUSR1R_FS_DVBINT0_Pos (23UL) /* DVBINT0 (Bit 23) */
1649#define RUSB2_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */
1650#define RUSB2_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /* DOVRCRB0 (Bit 21) */
1651#define RUSB2_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */
1652#define RUSB2_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /* DOVRCRA0 (Bit 20) */
1653#define RUSB2_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */
1654#define RUSB2_DPUSR1R_FS_DMINT0_Pos (17UL) /* DMINT0 (Bit 17) */
1655#define RUSB2_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /* DMINT0 (Bitfield-Mask: 0x01) */
1656#define RUSB2_DPUSR1R_FS_DPINT0_Pos (16UL) /* DPINT0 (Bit 16) */
1657#define RUSB2_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /* DPINT0 (Bitfield-Mask: 0x01) */
1658#define RUSB2_DPUSR1R_FS_DVBSE0_Pos (7UL) /* DVBSE0 (Bit 7) */
1659#define RUSB2_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /* DVBSE0 (Bitfield-Mask: 0x01) */
1660#define RUSB2_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /* DOVRCRBE0 (Bit 5) */
1661#define RUSB2_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /* DOVRCRBE0 (Bitfield-Mask: 0x01) */
1662#define RUSB2_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /* DOVRCRAE0 (Bit 4) */
1663#define RUSB2_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /* DOVRCRAE0 (Bitfield-Mask: 0x01) */
1664#define RUSB2_DPUSR1R_FS_DMINTE0_Pos (1UL) /* DMINTE0 (Bit 1) */
1665#define RUSB2_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /* DMINTE0 (Bitfield-Mask: 0x01) */
1666#define RUSB2_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */
1667#define RUSB2_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */
1668
1669/*--------------------------------------------------------------------*/
1670/* Register Bit Utils */
1671/*--------------------------------------------------------------------*/
1672#define RUSB2_PIPE_CTR_PID_NAK (0U << RUSB2_PIPE_CTR_PID_Pos) /* NAK response */
1673#define RUSB2_PIPE_CTR_PID_BUF (1U << RUSB2_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */
1674#define RUSB2_PIPE_CTR_PID_STALL (2U << RUSB2_PIPE_CTR_PID_Pos) /* STALL response */
1675#define RUSB2_PIPE_CTR_PID_STALL2 (3U << RUSB2_PIPE_CTR_PID_Pos) /* Also STALL response */
1676
1677#define RUSB2_DVSTCTR0_RHST_LS (1U << RUSB2_DVSTCTR0_RHST_Pos) /* Low-speed connection */
1678#define RUSB2_DVSTCTR0_RHST_FS (2U << RUSB2_DVSTCTR0_RHST_Pos) /* Full-speed connection */
1679#define RUSB2_DVSTCTR0_RHST_HS (3U << RUSB2_DVSTCTR0_RHST_Pos) /* Full-speed connection */
1680
1681#define RUSB2_DEVADD_USBSPD_LS (1U << RUSB2_DEVADD_USBSPD_Pos) /* Target Device Low-speed */
1682#define RUSB2_DEVADD_USBSPD_FS (2U << RUSB2_DEVADD_USBSPD_Pos) /* Target Device Full-speed */
1683
1684#define RUSB2_CFIFOSEL_ISEL_WRITE (1U << RUSB2_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/
1685
1686#define RUSB2_FIFOSEL_BIGEND (1U << RUSB2_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */
1687#define RUSB2_FIFOSEL_MBW_8BIT (0U << RUSB2_CFIFOSEL_MBW_Pos) /* 8-bit width */
1688#define RUSB2_FIFOSEL_MBW_16BIT (1U << RUSB2_CFIFOSEL_MBW_Pos) /* 16-bit width */
1689#define RUSB2_FIFOSEL_MBW_32BIT (2U << RUSB2_CFIFOSEL_MBW_Pos) /* 32-bit width */
1690
1691#define RUSB2_INTSTS0_CTSQ_CTRL_RDATA (1U << RUSB2_INTSTS0_CTSQ_Pos)
1692
1693#define RUSB2_INTSTS0_DVSQ_STATE_DEF (1U << RUSB2_INTSTS0_DVSQ_Pos) /* Default state */
1694#define RUSB2_INTSTS0_DVSQ_STATE_ADDR (2U << RUSB2_INTSTS0_DVSQ_Pos) /* Address state */
1695#define RUSB2_INTSTS0_DVSQ_STATE_SUSP0 (4U << RUSB2_INTSTS0_DVSQ_Pos) /* Suspend state */
1696#define RUSB2_INTSTS0_DVSQ_STATE_SUSP1 (5U << RUSB2_INTSTS0_DVSQ_Pos) /* Suspend state */
1697#define RUSB2_INTSTS0_DVSQ_STATE_SUSP2 (6U << RUSB2_INTSTS0_DVSQ_Pos) /* Suspend state */
1698#define RUSB2_INTSTS0_DVSQ_STATE_SUSP3 (7U << RUSB2_INTSTS0_DVSQ_Pos) /* Suspend state */
1699
1700#define RUSB2_PIPECFG_TYPE_BULK (1U << RUSB2_PIPECFG_TYPE_Pos)
1701#define RUSB2_PIPECFG_TYPE_INT (2U << RUSB2_PIPECFG_TYPE_Pos)
1702#define RUSB2_PIPECFG_TYPE_ISO (3U << RUSB2_PIPECFG_TYPE_Pos)
1703
1704//--------------------------------------------------------------------+
1705// Static Assert
1706//--------------------------------------------------------------------+
1707
1708TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size");
1709TU_VERIFY_STATIC(sizeof(rusb2_reg_t) == 1032, "incorrect size");
1710
1711TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSCFG ) == 0x0000, "incorrect offset");
1712TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BUSWAIT ) == 0x0002, "incorrect offset");
1713TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSSTS0 ) == 0x0004, "incorrect offset");
1714TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PLLSTA ) == 0x0006, "incorrect offset");
1715TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DVSTCTR0 ) == 0x0008, "incorrect offset");
1716TU_VERIFY_STATIC(offsetof(rusb2_reg_t, TESTMODE ) == 0x000C, "incorrect offset");
1717TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFO ) == 0x0014, "incorrect offset");
1718TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFO ) == 0x0018, "incorrect offset");
1719TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFO ) == 0x001C, "incorrect offset");
1720TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOSEL ) == 0x0020, "incorrect offset");
1721TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOCTR ) == 0x0022, "incorrect offset");
1722TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOSEL ) == 0x0028, "incorrect offset");
1723TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOCTR ) == 0x002A, "incorrect offset");
1724TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOSEL ) == 0x002C, "incorrect offset");
1725TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOCTR ) == 0x002E, "incorrect offset");
1726TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB0 ) == 0x0030, "incorrect offset");
1727TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB1 ) == 0x0032, "incorrect offset");
1728TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYENB ) == 0x0036, "incorrect offset");
1729TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYENB ) == 0x0038, "incorrect offset");
1730TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPENB ) == 0x003A, "incorrect offset");
1731TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SOFCFG ) == 0x003C, "incorrect offset");
1732TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSET ) == 0x003E, "incorrect offset");
1733TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS0 ) == 0x0040, "incorrect offset");
1734TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS1 ) == 0x0042, "incorrect offset");
1735TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYSTS ) == 0x0046, "incorrect offset");
1736TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYSTS ) == 0x0048, "incorrect offset");
1737TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPSTS ) == 0x004A, "incorrect offset");
1738TU_VERIFY_STATIC(offsetof(rusb2_reg_t, FRMNUM ) == 0x004C, "incorrect offset");
1739TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UFRMNUM ) == 0x004E, "incorrect offset");
1740TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBADDR ) == 0x0050, "incorrect offset");
1741TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBREQ ) == 0x0054, "incorrect offset");
1742TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBVAL ) == 0x0056, "incorrect offset");
1743TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBINDX ) == 0x0058, "incorrect offset");
1744TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBLENG ) == 0x005A, "incorrect offset");
1745TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCFG ) == 0x005C, "incorrect offset");
1746TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPMAXP ) == 0x005E, "incorrect offset");
1747TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCTR ) == 0x0060, "incorrect offset");
1748TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPESEL ) == 0x0064, "incorrect offset");
1749TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPECFG ) == 0x0068, "incorrect offset");
1750TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEBUF ) == 0x006A, "incorrect offset");
1751TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEMAXP ) == 0x006C, "incorrect offset");
1752TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEPERI ) == 0x006E, "incorrect offset");
1753TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_CTR ) == 0x0070, "incorrect offset");
1754TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_TR ) == 0x0090, "incorrect offset");
1755TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBBCCTRL0 ) == 0x00B0, "incorrect offset");
1756TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UCKSEL ) == 0x00C4, "incorrect offset");
1757TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBMC ) == 0x00CC, "incorrect offset");
1758TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DEVADD ) == 0x00D0, "incorrect offset");
1759TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSLEW ) == 0x00F0, "incorrect offset");
1760TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPCTRL ) == 0x0100, "incorrect offset");
1761TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPSTS ) == 0x0102, "incorrect offset");
1762TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BCCTRL ) == 0x0140, "incorrect offset");
1763TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL1 ) == 0x0144, "incorrect offset");
1764TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL2 ) == 0x0146, "incorrect offset");
1765TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL1 ) == 0x0148, "incorrect offset");
1766TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL2 ) == 0x014A, "incorrect offset");
1767TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM1 ) == 0x0150, "incorrect offset");
1768TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM2 ) == 0x0152, "incorrect offset");
1769TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R ) == 0x0160, "incorrect offset");
1770TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R ) == 0x0164, "incorrect offset");
1771TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR2R ) == 0x0168, "incorrect offset");
1772TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSRCR ) == 0x016A, "incorrect offset");
1773TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R_FS ) == 0x0400, "incorrect offset");
1774TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R_FS ) == 0x0404, "incorrect offset");
1775
1776#ifdef __cplusplus
1777}
1778#endif
1779
1780#endif /* _TUSB_RUSB2_TYPE_H_ */
reg_pipetre_t
TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN struct TU_ATTR_PACKED _ccrx_evenaccess reg_pipetre_t
rusb2_reg_t
struct _ccrx_evenaccess rusb2_reg_t
TU_VERIFY_STATIC
TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t)==4, "incorrect size")
_ccrx_evenaccess
Definition: rusb2_type.h:53
_ccrx_evenaccess::PIPEBUF
volatile uint16_t PIPEBUF
Definition: rusb2_type.h:672
_ccrx_evenaccess::DMRPU
volatile uint16_t DMRPU
Definition: rusb2_type.h:96
_ccrx_evenaccess::FIXPHY0
volatile uint32_t FIXPHY0
Definition: rusb2_type.h:982
_ccrx_evenaccess::DVCHG
volatile uint16_t DVCHG
Definition: rusb2_type.h:552
_ccrx_evenaccess::SLEWF01
volatile uint32_t SLEWF01
Definition: rusb2_type.h:790
_ccrx_evenaccess::UCKSELC
volatile uint16_t UCKSELC
Definition: rusb2_type.h:751
_ccrx_evenaccess::PIPE2BEMP
volatile uint16_t PIPE2BEMP
Definition: rusb2_type.h:523
_ccrx_evenaccess::PHYTRIM1_b
struct _ccrx_evenaccess::@568::@603 PHYTRIM1_b
_ccrx_evenaccess::BFRE
volatile uint16_t BFRE
Definition: rusb2_type.h:665
_ccrx_evenaccess::D0FIFOL
volatile uint16_t D0FIFOL
Definition: rusb2_type.h:195
_ccrx_evenaccess::HL1CTRL1_b
struct _ccrx_evenaccess::@564::TU_ATTR_PACKED HL1CTRL1_b
_ccrx_evenaccess::PHYTRIM1
volatile uint16_t PHYTRIM1
Definition: rusb2_type.h:887
_ccrx_evenaccess::PIPE0BEMP
volatile uint16_t PIPE0BEMP
Definition: rusb2_type.h:521
_ccrx_evenaccess::PIPE4NRDY
volatile uint16_t PIPE4NRDY
Definition: rusb2_type.h:507
_ccrx_evenaccess::BEMPE
volatile uint16_t BEMPE
Definition: rusb2_type.h:323
_ccrx_evenaccess::PIPESEL_b
struct _ccrx_evenaccess::@532::TU_ATTR_PACKED PIPESEL_b
_ccrx_evenaccess::CURPIPE
volatile uint16_t CURPIPE
Definition: rusb2_type.h:234
_ccrx_evenaccess::BRDYENB_b
struct _ccrx_evenaccess::@492::TU_ATTR_PACKED BRDYENB_b
_ccrx_evenaccess::PDDETSTS0
volatile const uint16_t PDDETSTS0
Definition: rusb2_type.h:740
_ccrx_evenaccess::BEMPSTS
volatile uint16_t BEMPSTS
Definition: rusb2_type.h:518
_ccrx_evenaccess::PIPE9BRDY
volatile uint16_t PIPE9BRDY
Definition: rusb2_type.h:494
_ccrx_evenaccess::BUSWAIT_b
struct _ccrx_evenaccess::@460::TU_ATTR_PACKED BUSWAIT_b
_ccrx_evenaccess::LNST
volatile const uint16_t LNST
Definition: rusb2_type.h:121
_ccrx_evenaccess::ATREPM
volatile uint16_t ATREPM
Definition: rusb2_type.h:714
_ccrx_evenaccess::FRMNUM_b
struct _ccrx_evenaccess::@512::TU_ATTR_PACKED FRMNUM_b
_ccrx_evenaccess::SHTNAK
volatile uint16_t SHTNAK
Definition: rusb2_type.h:608
_ccrx_evenaccess::HTACT
volatile const uint16_t HTACT
Definition: rusb2_type.h:125
_ccrx_evenaccess::DTCHE
volatile uint16_t DTCHE
Definition: rusb2_type.h:346
_ccrx_evenaccess::RESERVED4
volatile const uint8_t RESERVED4
Definition: rusb2_type.h:203
_ccrx_evenaccess::CFIFOHH
volatile uint8_t CFIFOHH
Definition: rusb2_type.h:184
_ccrx_evenaccess::PIPE8BRDY
volatile uint16_t PIPE8BRDY
Definition: rusb2_type.h:493
_ccrx_evenaccess::USBADDR
volatile const uint16_t USBADDR
Definition: rusb2_type.h:560
_ccrx_evenaccess::PIPE2NRDY
volatile uint16_t PIPE2NRDY
Definition: rusb2_type.h:505
_ccrx_evenaccess::PIPE5BRDY
volatile uint16_t PIPE5BRDY
Definition: rusb2_type.h:490
_ccrx_evenaccess::DBLB
volatile uint16_t DBLB
Definition: rusb2_type.h:664
_ccrx_evenaccess::TESTMODE
volatile uint16_t TESTMODE
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_ccrx_evenaccess::DPINT0
volatile const uint32_t DPINT0
Definition: rusb2_type.h:1007
_ccrx_evenaccess::UPPHUB
volatile uint16_t UPPHUB
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_ccrx_evenaccess::DEVADD
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Definition: rusb2_type.h:771
_ccrx_evenaccess::UFRNM
volatile const uint16_t UFRNM
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_ccrx_evenaccess::IDPSINKE
volatile uint16_t IDPSINKE
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_ccrx_evenaccess::TRE
uint16_t TRE
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_ccrx_evenaccess::RESERVED18
volatile const uint16_t RESERVED18
Definition: rusb2_type.h:755
_ccrx_evenaccess::LPSTS
volatile uint16_t LPSTS
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_ccrx_evenaccess::HL1CTRL1
volatile uint16_t HL1CTRL1
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_ccrx_evenaccess::DPUSR1R
volatile uint32_t DPUSR1R
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_ccrx_evenaccess::HSRXENMO
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volatile const uint16_t PLLLOCK
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_ccrx_evenaccess::USBMC
volatile uint16_t USBMC
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_ccrx_evenaccess::DOVCBHE
volatile uint32_t DOVCBHE
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_ccrx_evenaccess::PIPE3BEMPE
volatile uint16_t PIPE3BEMPE
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_ccrx_evenaccess::VDPSRCE
volatile uint16_t VDPSRCE
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_ccrx_evenaccess::HL1CTRL2_b
struct _ccrx_evenaccess::@566::TU_ATTR_PACKED HL1CTRL2_b
_ccrx_evenaccess::TRCLR
uint16_t TRCLR
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_ccrx_evenaccess::PIPE0NRDYE
volatile uint16_t PIPE0NRDYE
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_ccrx_evenaccess::IMPOFFSET
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volatile uint32_t D1FIFO
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_ccrx_evenaccess::INTSTS1_b
struct _ccrx_evenaccess::@504::TU_ATTR_PACKED INTSTS1_b
_ccrx_evenaccess::IDMSINKE0
volatile uint16_t IDMSINKE0
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_ccrx_evenaccess::WLENGTH
volatile uint16_t WLENGTH
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_ccrx_evenaccess::LPMENDE
volatile uint16_t LPMENDE
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_ccrx_evenaccess::CFIFOH
volatile uint16_t CFIFOH
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_ccrx_evenaccess::DCLRM
volatile uint16_t DCLRM
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_ccrx_evenaccess::TESTMODE_b
struct _ccrx_evenaccess::@468::TU_ATTR_PACKED TESTMODE_b
_ccrx_evenaccess::VALID
volatile uint16_t VALID
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_ccrx_evenaccess::SRPC0
volatile uint32_t SRPC0
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_ccrx_evenaccess::DOVCA0
volatile const uint32_t DOVCA0
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_ccrx_evenaccess::USBINDX
volatile uint16_t USBINDX
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_ccrx_evenaccess::PHYSET_b
struct _ccrx_evenaccess::@500::TU_ATTR_PACKED PHYSET_b
_ccrx_evenaccess::L1RESPMD
volatile uint16_t L1RESPMD
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_ccrx_evenaccess::DCPCTR
volatile uint16_t DCPCTR
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_ccrx_evenaccess::PIPE8BRDYE
volatile uint16_t PIPE8BRDYE
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_ccrx_evenaccess::D0FIFOSEL
volatile uint16_t D0FIFOSEL
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_ccrx_evenaccess::DVSTCTR0
volatile uint16_t DVSTCTR0
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_ccrx_evenaccess::LPMEND
volatile uint16_t LPMEND
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_ccrx_evenaccess::CNEN
volatile uint16_t CNEN
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_ccrx_evenaccess::RESERVED9
volatile const uint16_t RESERVED9
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_ccrx_evenaccess::PIPE6BEMP
volatile uint16_t PIPE6BEMP
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_ccrx_evenaccess::IDPSINKE0
volatile uint16_t IDPSINKE0
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_ccrx_evenaccess::PIPESEL
volatile uint16_t PIPESEL
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_ccrx_evenaccess::DOVRCRB0
volatile const uint32_t DOVRCRB0
Definition: rusb2_type.h:1011
_ccrx_evenaccess::PL1CTRL1
volatile uint16_t PL1CTRL1
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_ccrx_evenaccess::BUFNMB
volatile uint16_t BUFNMB
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_ccrx_evenaccess::DOVCAH
volatile const uint32_t DOVCAH
Definition: rusb2_type.h:938
_ccrx_evenaccess::DCPMODE
volatile uint16_t DCPMODE
Definition: rusb2_type.h:826
_ccrx_evenaccess::SOFCFG
volatile uint16_t SOFCFG
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_ccrx_evenaccess::PIPE1NRDY
volatile uint16_t PIPE1NRDY
Definition: rusb2_type.h:504
_ccrx_evenaccess::DTCH
volatile uint16_t DTCH
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_ccrx_evenaccess::DPUSR1R_FS
volatile uint32_t DPUSR1R_FS
Definition: rusb2_type.h:996
_ccrx_evenaccess::SACK
volatile uint16_t SACK
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_ccrx_evenaccess::PIPE1BEMPE
volatile uint16_t PIPE1BEMPE
Definition: rusb2_type.h:395
_ccrx_evenaccess::PLLSTA
volatile const uint16_t PLLSTA
Definition: rusb2_type.h:132
_ccrx_evenaccess::DVSQ
volatile const uint16_t DVSQ
Definition: rusb2_type.h:446
_ccrx_evenaccess::PL1CTRL2
volatile uint16_t PL1CTRL2
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_ccrx_evenaccess::UFRMNUM
volatile uint16_t UFRMNUM
Definition: rusb2_type.h:547
_ccrx_evenaccess::PIPE1BEMP
volatile uint16_t PIPE1BEMP
Definition: rusb2_type.h:522
_ccrx_evenaccess::BCHGE
volatile uint16_t BCHGE
Definition: rusb2_type.h:348
_ccrx_evenaccess::CFIFO
volatile uint32_t CFIFO
Definition: rusb2_type.h:171
_ccrx_evenaccess::RESERVED8
volatile const uint16_t RESERVED8
Definition: rusb2_type.h:479
_ccrx_evenaccess::WVALUE
volatile uint16_t WVALUE
Definition: rusb2_type.h:581
_ccrx_evenaccess::HIRDMON
volatile uint16_t HIRDMON
Definition: rusb2_type.h:855
_ccrx_evenaccess::RHST
volatile const uint16_t RHST
Definition: rusb2_type.h:144
_ccrx_evenaccess::PIPE6NRDYE
volatile uint16_t PIPE6NRDYE
Definition: rusb2_type.h:382
_ccrx_evenaccess::HSE
volatile uint16_t HSE
Definition: rusb2_type.h:100
_ccrx_evenaccess::D1FIFOCTR_b
struct _ccrx_evenaccess::@486::TU_ATTR_PACKED D1FIFOCTR_b
_ccrx_evenaccess::BCLR
volatile uint16_t BCLR
Definition: rusb2_type.h:254
_ccrx_evenaccess::CFIFOL
volatile uint16_t CFIFOL
Definition: rusb2_type.h:175
_ccrx_evenaccess::UACT
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Definition: rusb2_type.h:146
_ccrx_evenaccess::RESERVED1
volatile const uint16_t RESERVED1
Definition: rusb2_type.h:167
_ccrx_evenaccess::PIPEMAXP_b
struct _ccrx_evenaccess::@538::TU_ATTR_PACKED PIPEMAXP_b
_ccrx_evenaccess::PIPEMAXP
volatile uint16_t PIPEMAXP
Definition: rusb2_type.h:683
_ccrx_evenaccess::FIXPHY
volatile uint16_t FIXPHY
Definition: rusb2_type.h:966
_ccrx_evenaccess::VBUSEN
volatile uint16_t VBUSEN
Definition: rusb2_type.h:151
_ccrx_evenaccess::PL1CTRL1_b
struct _ccrx_evenaccess::@560::TU_ATTR_PACKED PL1CTRL1_b
_ccrx_evenaccess::CTSQ
volatile const uint16_t CTSQ
Definition: rusb2_type.h:444
_ccrx_evenaccess::PHYSLEW_b
struct _ccrx_evenaccess::@552::TU_ATTR_PACKED PHYSLEW_b
_ccrx_evenaccess::L1EXTMD
volatile uint16_t L1EXTMD
Definition: rusb2_type.h:845
_ccrx_evenaccess::USBADDR
volatile uint16_t USBADDR
Definition: rusb2_type.h:557
_ccrx_evenaccess::CFIFOCTR_b
struct _ccrx_evenaccess::@478::TU_ATTR_PACKED CFIFOCTR_b
_ccrx_evenaccess::RESERVED2
volatile const uint32_t RESERVED2
Definition: rusb2_type.h:168
_ccrx_evenaccess::PIPE3BRDY
volatile uint16_t PIPE3BRDY
Definition: rusb2_type.h:488
_ccrx_evenaccess::L1STATUS
volatile const uint16_t L1STATUS
Definition: rusb2_type.h:866
_ccrx_evenaccess::RESERVED25_2
volatile uint32_t RESERVED25_2[3]
Definition: rusb2_type.h:913
_ccrx_evenaccess::DIR
volatile uint16_t DIR
Definition: rusb2_type.h:606
_ccrx_evenaccess::VDMSRCE
volatile uint16_t VDMSRCE
Definition: rusb2_type.h:825
_ccrx_evenaccess::RESERVED22
volatile const uint32_t RESERVED22[3]
Definition: rusb2_type.h:794
_ccrx_evenaccess::EOFERR
volatile uint16_t EOFERR
Definition: rusb2_type.h:467
_ccrx_evenaccess::PDDETINT0
volatile uint16_t PDDETINT0
Definition: rusb2_type.h:463
_ccrx_evenaccess::D0FIFOHH
volatile uint8_t D0FIFOHH
Definition: rusb2_type.h:204
_ccrx_evenaccess::BUSWAIT
volatile uint16_t BUSWAIT
Definition: rusb2_type.h:109
_ccrx_evenaccess::VBSTS
volatile const uint16_t VBSTS
Definition: rusb2_type.h:447
_ccrx_evenaccess::BWAIT
volatile uint16_t BWAIT
Definition: rusb2_type.h:112
_ccrx_evenaccess::PHYTRIM2_b
struct _ccrx_evenaccess::@570::@604 PHYTRIM2_b
_ccrx_evenaccess::CFIFOSEL
volatile uint16_t CFIFOSEL
Definition: rusb2_type.h:231
_ccrx_evenaccess::RESERVED20
volatile const uint16_t RESERVED20
Definition: rusb2_type.h:768
_ccrx_evenaccess::D1FIFOH
volatile uint16_t D1FIFOH
Definition: rusb2_type.h:220
_ccrx_evenaccess::INTENB1
volatile uint16_t INTENB1
Definition: rusb2_type.h:333
_ccrx_evenaccess::PL1CTRL2_b
struct _ccrx_evenaccess::@562::TU_ATTR_PACKED PL1CTRL2_b
_ccrx_evenaccess::RESERVED19
volatile const uint32_t RESERVED19
Definition: rusb2_type.h:756
_ccrx_evenaccess::PIPE2BRDY
volatile uint16_t PIPE2BRDY
Definition: rusb2_type.h:487
_ccrx_evenaccess::PIPE9NRDY
volatile uint16_t PIPE9NRDY
Definition: rusb2_type.h:512
_ccrx_evenaccess::NRDYE
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Definition: rusb2_type.h:322
_ccrx_evenaccess::PIPE7BRDY
volatile uint16_t PIPE7BRDY
Definition: rusb2_type.h:492
_ccrx_evenaccess::VBSE
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Definition: rusb2_type.h:328
_ccrx_evenaccess::SYSSTS0_b
struct _ccrx_evenaccess::@462::TU_ATTR_PACKED SYSSTS0_b
_ccrx_evenaccess::PIPE8BEMP
volatile uint16_t PIPE8BEMP
Definition: rusb2_type.h:529
_ccrx_evenaccess::DCPCTR_b
struct _ccrx_evenaccess::@530::TU_ATTR_PACKED DCPCTR_b
_ccrx_evenaccess::IDPSRCE0
volatile uint16_t IDPSRCE0
Definition: rusb2_type.h:732
_ccrx_evenaccess::DOVCAHM
volatile const uint32_t DOVCAHM
Definition: rusb2_type.h:920
_ccrx_evenaccess::DPINT
volatile const uint16_t DPINT
Definition: rusb2_type.h:950
_ccrx_evenaccess::ISEL
volatile uint16_t ISEL
Definition: rusb2_type.h:236
_ccrx_evenaccess::SLEWF00
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Definition: rusb2_type.h:789
_ccrx_evenaccess::DPINTE0
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Definition: rusb2_type.h:999
_ccrx_evenaccess::DVBINT0
volatile const uint32_t DVBINT0
Definition: rusb2_type.h:1013
_ccrx_evenaccess::RESERVED24
volatile const uint16_t RESERVED24
Definition: rusb2_type.h:833
_ccrx_evenaccess::SLEWR01
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Definition: rusb2_type.h:788
_ccrx_evenaccess::DCPMAXP
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Definition: rusb2_type.h:615
_ccrx_evenaccess::USBBCCTRL0
volatile uint16_t USBBCCTRL0
Definition: rusb2_type.h:728
_ccrx_evenaccess::D0FIFO
volatile uint32_t D0FIFO
Definition: rusb2_type.h:191
_ccrx_evenaccess::PDR
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Definition: rusb2_type.h:907
_ccrx_evenaccess::PIPE8NRDY
volatile uint16_t PIPE8NRDY
Definition: rusb2_type.h:511
_ccrx_evenaccess::CHGDETSTS
volatile const uint16_t CHGDETSTS
Definition: rusb2_type.h:828
_ccrx_evenaccess::RESUME
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Definition: rusb2_type.h:147
_ccrx_evenaccess::PHYSET
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Definition: rusb2_type.h:423
_ccrx_evenaccess::PIPE2NRDYE
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Definition: rusb2_type.h:378
_ccrx_evenaccess::DPVAL
volatile const uint16_t DPVAL
Definition: rusb2_type.h:953
_ccrx_evenaccess::DMVAL
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Definition: rusb2_type.h:954
_ccrx_evenaccess::D0FIFOH
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Definition: rusb2_type.h:200
_ccrx_evenaccess::DVBSTS0
volatile const uint32_t DVBSTS0
Definition: rusb2_type.h:990
_ccrx_evenaccess::CFIFOSEL_b
struct _ccrx_evenaccess::@476::TU_ATTR_PACKED CFIFOSEL_b
_ccrx_evenaccess::BUFSIZE
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Definition: rusb2_type.h:677
_ccrx_evenaccess::TRNENSEL
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Definition: rusb2_type.h:417
_ccrx_evenaccess::NRDY
volatile const uint16_t NRDY
Definition: rusb2_type.h:449
_ccrx_evenaccess::LPSTS_b
struct _ccrx_evenaccess::@556::TU_ATTR_PACKED LPSTS_b
_ccrx_evenaccess::EOFERRE
volatile uint16_t EOFERRE
Definition: rusb2_type.h:340
_ccrx_evenaccess::L1RSMENDE
volatile uint16_t L1RSMENDE
Definition: rusb2_type.h:343
_ccrx_evenaccess::D1FIFOCTR
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Definition: rusb2_type.h:305
_ccrx_evenaccess::SQCLR
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Definition: rusb2_type.h:634
_ccrx_evenaccess::PIPE4NRDYE
volatile uint16_t PIPE4NRDYE
Definition: rusb2_type.h:380
_ccrx_evenaccess::VDCEN
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Definition: rusb2_type.h:764
_ccrx_evenaccess::BRDYM
volatile uint16_t BRDYM
Definition: rusb2_type.h:415
_ccrx_evenaccess::UCKSEL_b
struct _ccrx_evenaccess::@546::TU_ATTR_PACKED UCKSEL_b
_ccrx_evenaccess::NRDYSTS
volatile uint16_t NRDYSTS
Definition: rusb2_type.h:500
_ccrx_evenaccess::PIPE4BEMPE
volatile uint16_t PIPE4BEMPE
Definition: rusb2_type.h:398
_ccrx_evenaccess::PIPE1BRDYE
volatile uint16_t PIPE1BRDYE
Definition: rusb2_type.h:359
_ccrx_evenaccess::SQMON
volatile const uint16_t SQMON
Definition: rusb2_type.h:632
_ccrx_evenaccess::D0FIFOCTR_b
struct _ccrx_evenaccess::@482::TU_ATTR_PACKED D0FIFOCTR_b
_ccrx_evenaccess::USBADDR_b
struct _ccrx_evenaccess::@516::TU_ATTR_PACKED USBADDR_b
_ccrx_evenaccess::PIPE6NRDY
volatile uint16_t PIPE6NRDY
Definition: rusb2_type.h:509
_ccrx_evenaccess::NRDYENB_b
struct _ccrx_evenaccess::@494::TU_ATTR_PACKED NRDYENB_b
_ccrx_evenaccess::BATCHGE0
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Definition: rusb2_type.h:738
_ccrx_evenaccess::DRISE
volatile uint16_t DRISE
Definition: rusb2_type.h:890
_ccrx_evenaccess::D1FIFOSEL
volatile uint16_t D1FIFOSEL
Definition: rusb2_type.h:289
_ccrx_evenaccess::DOVRCRA0
volatile const uint32_t DOVRCRA0
Definition: rusb2_type.h:1010
_ccrx_evenaccess::L1REQ
volatile uint16_t L1REQ
Definition: rusb2_type.h:865
_ccrx_evenaccess::REW
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Definition: rusb2_type.h:242
_ccrx_evenaccess::OVCMON
volatile const uint16_t OVCMON
Definition: rusb2_type.h:127
_ccrx_evenaccess::PIPE_TR
volatile RUSB2_PIPE_TR_t PIPE_TR[5]
Definition: rusb2_type.h:724
_ccrx_evenaccess::OVRCR
volatile uint16_t OVRCR
Definition: rusb2_type.h:476
_ccrx_evenaccess::PBUSY
volatile const uint16_t PBUSY
Definition: rusb2_type.h:631
_ccrx_evenaccess::DIS
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Definition: rusb2_type.h:909
_ccrx_evenaccess::SOFEA
volatile const uint16_t SOFEA
Definition: rusb2_type.h:124
_ccrx_evenaccess::RESERVED23
volatile const uint32_t RESERVED23[15]
Definition: rusb2_type.h:815
_ccrx_evenaccess::INTSTS0_b
struct _ccrx_evenaccess::@502::TU_ATTR_PACKED INTSTS0_b
_ccrx_evenaccess::RESERVED15
volatile const uint32_t RESERVED15[3]
Definition: rusb2_type.h:725
_ccrx_evenaccess::PDDETINTE0
volatile uint16_t PDDETINTE0
Definition: rusb2_type.h:336
_ccrx_evenaccess::PIPE5BEMPE
volatile uint16_t PIPE5BEMPE
Definition: rusb2_type.h:399
_ccrx_evenaccess::RESERVED21
volatile const uint32_t RESERVED21[3]
Definition: rusb2_type.h:781
_ccrx_evenaccess::STSRECOV0
volatile uint16_t STSRECOV0
Definition: rusb2_type.h:562
_ccrx_evenaccess::VDMSRCE0
volatile uint16_t VDMSRCE0
Definition: rusb2_type.h:736
_ccrx_evenaccess::USBVAL_b
struct _ccrx_evenaccess::@520::TU_ATTR_PACKED USBVAL_b
_ccrx_evenaccess::USBLENG
volatile uint16_t USBLENG
Definition: rusb2_type.h:594
_ccrx_evenaccess::INTSTS0
volatile uint16_t INTSTS0
Definition: rusb2_type.h:441
_ccrx_evenaccess::INTENB1_b
struct _ccrx_evenaccess::@490::TU_ATTR_PACKED INTENB1_b
_ccrx_evenaccess::DP0
volatile const uint32_t DP0
Definition: rusb2_type.h:984
_ccrx_evenaccess::DIRPD
volatile uint16_t DIRPD
Definition: rusb2_type.h:426
_ccrx_evenaccess::PIPE_CTR
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Definition: rusb2_type.h:704
_ccrx_evenaccess::RESERVED11
volatile const uint16_t RESERVED11
Definition: rusb2_type.h:653
_ccrx_evenaccess::SOFCFG_b
struct _ccrx_evenaccess::@498::TU_ATTR_PACKED SOFCFG_b
_ccrx_evenaccess::SOFR
volatile uint16_t SOFR
Definition: rusb2_type.h:453
_ccrx_evenaccess::PIPE9NRDYE
volatile uint16_t PIPE9NRDYE
Definition: rusb2_type.h:385
_ccrx_evenaccess::RESERVED25_1
volatile uint32_t RESERVED25_1
Definition: rusb2_type.h:884
_ccrx_evenaccess::D1FIFOL
volatile uint16_t D1FIFOL
Definition: rusb2_type.h:215
_ccrx_evenaccess::UTST
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Definition: rusb2_type.h:163
_ccrx_evenaccess::NRDYENB
volatile uint16_t NRDYENB
Definition: rusb2_type.h:373
_ccrx_evenaccess::SQSET
volatile uint16_t SQSET
Definition: rusb2_type.h:633
_ccrx_evenaccess::PLLRESET
volatile uint16_t PLLRESET
Definition: rusb2_type.h:427
_ccrx_evenaccess::BMREQUESTTYPE
volatile uint16_t BMREQUESTTYPE
Definition: rusb2_type.h:572
_ccrx_evenaccess::CLKSEL
volatile uint16_t CLKSEL
Definition: rusb2_type.h:430
_ccrx_evenaccess::DPUSR1R_FS_b
struct _ccrx_evenaccess::@582::TU_ATTR_PACKED DPUSR1R_FS_b
_ccrx_evenaccess::PIPE4BRDYE
volatile uint16_t PIPE4BRDYE
Definition: rusb2_type.h:362
_ccrx_evenaccess::ACLRM
volatile uint16_t ACLRM
Definition: rusb2_type.h:713
_ccrx_evenaccess::BEMP
volatile const uint16_t BEMP
Definition: rusb2_type.h:450
_ccrx_evenaccess::SUSPENDM
volatile uint16_t SUSPENDM
Definition: rusb2_type.h:811
_ccrx_evenaccess::RESERVED6
volatile const uint32_t RESERVED6
Definition: rusb2_type.h:258
_ccrx_evenaccess::DOVCBHM
volatile const uint32_t DOVCBHM
Definition: rusb2_type.h:921
_ccrx_evenaccess::HL1CTRL2
volatile uint16_t HL1CTRL2
Definition: rusb2_type.h:872
_ccrx_evenaccess::RPUE0
volatile uint32_t RPUE0
Definition: rusb2_type.h:979
_ccrx_evenaccess::PIPE4BEMP
volatile uint16_t PIPE4BEMP
Definition: rusb2_type.h:525
_ccrx_evenaccess::USBE
volatile uint16_t USBE
Definition: rusb2_type.h:94
_ccrx_evenaccess::PIPE1NRDYE
volatile uint16_t PIPE1NRDYE
Definition: rusb2_type.h:377
_ccrx_evenaccess::DMINT
volatile const uint16_t DMINT
Definition: rusb2_type.h:951
_ccrx_evenaccess::USBREQ
volatile uint16_t USBREQ
Definition: rusb2_type.h:569
_ccrx_evenaccess::EDGESTS
volatile const uint16_t EDGESTS
Definition: rusb2_type.h:413
_ccrx_evenaccess::VDPSRCE0
volatile uint16_t VDPSRCE0
Definition: rusb2_type.h:734
_ccrx_evenaccess::CHGDETSTS0
volatile const uint16_t CHGDETSTS0
Definition: rusb2_type.h:739
_ccrx_evenaccess::RESERVED5
volatile const uint8_t RESERVED5
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_ccrx_evenaccess::CSCLR
volatile uint16_t CSCLR
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_ccrx_evenaccess::UCKSEL
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_ccrx_evenaccess::PIPECFG
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_ccrx_evenaccess::PIPE5NRDYE
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_ccrx_evenaccess::BRDY
volatile const uint16_t BRDY
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_ccrx_evenaccess::RWEMON
volatile uint16_t RWEMON
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_ccrx_evenaccess::BVAL
volatile uint16_t BVAL
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_ccrx_evenaccess::USBREQ_b
struct _ccrx_evenaccess::@518::TU_ATTR_PACKED USBREQ_b
_ccrx_evenaccess::D0FIFOSEL_b
struct _ccrx_evenaccess::@480::TU_ATTR_PACKED D0FIFOSEL_b
_ccrx_evenaccess::HNPBTOA
volatile uint16_t HNPBTOA
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_ccrx_evenaccess::SUREQCLR
volatile uint16_t SUREQCLR
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volatile const uint16_t CSSTS
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volatile uint16_t SYSCFG
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_ccrx_evenaccess::ATTCH
volatile uint16_t ATTCH
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_ccrx_evenaccess::CSSTS
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_ccrx_evenaccess::DPUSR0R_FS
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_ccrx_evenaccess::USBBCCTRL0_b
struct _ccrx_evenaccess::@544::TU_ATTR_PACKED USBBCCTRL0_b
_ccrx_evenaccess::USBINDX_b
struct _ccrx_evenaccess::@522::TU_ATTR_PACKED USBINDX_b
_ccrx_evenaccess::DPUSR2R
volatile uint16_t DPUSR2R
Definition: rusb2_type.h:947
_ccrx_evenaccess::ATTCHE
volatile uint16_t ATTCHE
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_ccrx_evenaccess::DEVSEL
volatile uint16_t DEVSEL
Definition: rusb2_type.h:620
_ccrx_evenaccess::DOVRCRBE0
volatile uint32_t DOVRCRBE0
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_ccrx_evenaccess::CRCE
volatile uint16_t CRCE
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_ccrx_evenaccess::DCFM
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_ccrx_evenaccess::DPRPU
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_ccrx_evenaccess::PIPE0BEMPE
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_ccrx_evenaccess::RESERVED3
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_ccrx_evenaccess::DVSTCTR0_b
struct _ccrx_evenaccess::@466::TU_ATTR_PACKED DVSTCTR0_b
_ccrx_evenaccess::UFRMNUM_b
struct _ccrx_evenaccess::@514::TU_ATTR_PACKED UFRMNUM_b
_ccrx_evenaccess::PIPEPERI_b
struct _ccrx_evenaccess::@540::TU_ATTR_PACKED PIPEPERI_b
_ccrx_evenaccess::PIPE0NRDY
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volatile const uint32_t DMINT0
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_ccrx_evenaccess::OVRN
volatile uint16_t OVRN
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_ccrx_evenaccess::RSME
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_ccrx_evenaccess::DVBSTSHM
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_ccrx_evenaccess::BEMPENB_b
struct _ccrx_evenaccess::@496::TU_ATTR_PACKED BEMPENB_b
_ccrx_evenaccess::SYSCFG_b
struct _ccrx_evenaccess::@458::TU_ATTR_PACKED SYSCFG_b
_ccrx_evenaccess::DPUSRCR
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_ccrx_evenaccess::DMINTE0
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_ccrx_evenaccess::SYSSTS0
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_ccrx_evenaccess::BEMPENB
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Definition: rusb2_type.h:391
_ccrx_evenaccess::CTRE
volatile uint16_t CTRE
Definition: rusb2_type.h:324
_ccrx_evenaccess::PID
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_ccrx_evenaccess::PIPE3BRDYE
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_ccrx_evenaccess::DOVCAHE
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Definition: rusb2_type.h:933
_ccrx_evenaccess::FRDY
volatile const uint16_t FRDY
Definition: rusb2_type.h:253
_ccrx_evenaccess::EXICEN
volatile uint16_t EXICEN
Definition: rusb2_type.h:152
_ccrx_evenaccess::DVBSTSHE
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Definition: rusb2_type.h:936
_ccrx_evenaccess::HSEB
volatile uint16_t HSEB
Definition: rusb2_type.h:436
_ccrx_evenaccess::D0FIFOCTR
volatile uint16_t D0FIFOCTR
Definition: rusb2_type.h:277
_ccrx_evenaccess::RESERVED14
volatile const uint32_t RESERVED14[3]
Definition: rusb2_type.h:723
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volatile uint32_t PHYSLEW
Definition: rusb2_type.h:784
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volatile uint16_t L1RWE
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_ccrx_evenaccess::HIRDTHR
volatile uint16_t HIRDTHR
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_ccrx_evenaccess::TRN
uint16_t TRN
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_ccrx_evenaccess::HUBPORT
volatile uint16_t HUBPORT
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_ccrx_evenaccess::IDMSINKE
volatile uint16_t IDMSINKE
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_ccrx_evenaccess::PIPE7NRDYE
volatile uint16_t PIPE7NRDYE
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_ccrx_evenaccess::EPNUM
volatile uint16_t EPNUM
Definition: rusb2_type.h:659
_ccrx_evenaccess::PIPE8NRDYE
volatile uint16_t PIPE8NRDYE
Definition: rusb2_type.h:384
_ccrx_evenaccess::HSIUP
volatile uint16_t HSIUP
Definition: rusb2_type.h:894
_ccrx_evenaccess::RESERVED7
volatile const uint16_t RESERVED7
Definition: rusb2_type.h:352
_ccrx_evenaccess::PIPE7BEMPE
volatile uint16_t PIPE7BEMPE
Definition: rusb2_type.h:401
_ccrx_evenaccess::PIPE6BRDY
volatile uint16_t PIPE6BRDY
Definition: rusb2_type.h:491
_ccrx_evenaccess::DRPD
volatile uint16_t DRPD
Definition: rusb2_type.h:98
_ccrx_evenaccess::DPUSR2R_b
struct _ccrx_evenaccess::@576::TU_ATTR_PACKED DPUSR2R_b
_ccrx_evenaccess::CTRT
volatile uint16_t CTRT
Definition: rusb2_type.h:451
_ccrx_evenaccess::RESERVED26
volatile const uint32_t RESERVED26[165]
Definition: rusb2_type.h:971
_ccrx_evenaccess::LPCTRL_b
struct _ccrx_evenaccess::@554::TU_ATTR_PACKED LPCTRL_b
_ccrx_evenaccess::DCPCFG_b
struct _ccrx_evenaccess::@526::TU_ATTR_PACKED DCPCFG_b
_ccrx_evenaccess::DPUSR0R_FS_b
struct _ccrx_evenaccess::@580::TU_ATTR_PACKED DPUSR0R_FS_b
_ccrx_evenaccess::LPCTRL
volatile uint16_t LPCTRL
Definition: rusb2_type.h:797
_ccrx_evenaccess::OVRCRE
volatile uint16_t OVRCRE
Definition: rusb2_type.h:349
_ccrx_evenaccess::PIPE1BRDY
volatile uint16_t PIPE1BRDY
Definition: rusb2_type.h:486
_ccrx_evenaccess::DPINTE
volatile uint16_t DPINTE
Definition: rusb2_type.h:956
_ccrx_evenaccess::CFIFOCTR
volatile uint16_t CFIFOCTR
Definition: rusb2_type.h:248
_ccrx_evenaccess::PIPECFG_b
struct _ccrx_evenaccess::@534::TU_ATTR_PACKED PIPECFG_b
_ccrx_evenaccess::BRDYE
volatile uint16_t BRDYE
Definition: rusb2_type.h:321
_ccrx_evenaccess::PIPE5BEMP
volatile uint16_t PIPE5BEMP
Definition: rusb2_type.h:526
_ccrx_evenaccess::HWUPM
volatile uint16_t HWUPM
Definition: rusb2_type.h:801
_ccrx_evenaccess::DM0
volatile const uint32_t DM0
Definition: rusb2_type.h:985
_ccrx_evenaccess::DRPD0
volatile uint32_t DRPD0
Definition: rusb2_type.h:981
_ccrx_evenaccess::L1NEGOMD
volatile uint16_t L1NEGOMD
Definition: rusb2_type.h:841
_ccrx_evenaccess::PIPE6BRDYE
volatile uint16_t PIPE6BRDYE
Definition: rusb2_type.h:364
_ccrx_evenaccess::WKUP
volatile uint16_t WKUP
Definition: rusb2_type.h:150
_ccrx_evenaccess::D1FIFOLL
volatile uint8_t D1FIFOLL
Definition: rusb2_type.h:216
_ccrx_evenaccess::BIGEND
volatile uint16_t BIGEND
Definition: rusb2_type.h:238
_ccrx_evenaccess::RESERVED17
volatile const uint32_t RESERVED17[4]
Definition: rusb2_type.h:745
_ccrx_evenaccess::DPUSRCR_b
struct _ccrx_evenaccess::@578::TU_ATTR_PACKED DPUSRCR_b
_ccrx_evenaccess::DPUSR0R_b
struct _ccrx_evenaccess::@572::TU_ATTR_PACKED DPUSR0R_b
_ccrx_evenaccess::PIPE_CTR_b
struct _ccrx_evenaccess::@542::TU_ATTR_PACKED PIPE_CTR_b[9]
_ccrx_evenaccess::DEVADD_b
struct _ccrx_evenaccess::@550::TU_ATTR_PACKED DEVADD_b[10]
_ccrx_evenaccess::VDDUSBE
volatile uint16_t VDDUSBE
Definition: rusb2_type.h:762
_ccrx_evenaccess::L1RESPEN
volatile uint16_t L1RESPEN
Definition: rusb2_type.h:839
_ccrx_evenaccess::CDPEN
volatile uint16_t CDPEN
Definition: rusb2_type.h:429
_ccrx_evenaccess::USBSPD
volatile uint16_t USBSPD
Definition: rusb2_type.h:775
_ccrx_evenaccess::INTSTS1
volatile uint16_t INTSTS1
Definition: rusb2_type.h:460
_ccrx_evenaccess::DOVCB0
volatile const uint32_t DOVCB0
Definition: rusb2_type.h:988
_ccrx_evenaccess::PIPE9BEMPE
volatile uint16_t PIPE9BEMPE
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_ccrx_evenaccess::BRDYSTS
volatile uint16_t BRDYSTS
Definition: rusb2_type.h:482
_ccrx_evenaccess::PIPE3BEMP
volatile uint16_t PIPE3BEMP
Definition: rusb2_type.h:524
_ccrx_evenaccess::SUREQ
volatile uint16_t SUREQ
Definition: rusb2_type.h:639
_ccrx_evenaccess::D1FIFOSEL_b
struct _ccrx_evenaccess::@484::TU_ATTR_PACKED D1FIFOSEL_b
_ccrx_evenaccess::USBRST
volatile uint16_t USBRST
Definition: rusb2_type.h:148
_ccrx_evenaccess::BREQUEST
volatile uint16_t BREQUEST
Definition: rusb2_type.h:573
_ccrx_evenaccess::DPUSR0R
volatile const uint32_t DPUSR0R
Definition: rusb2_type.h:916
_ccrx_evenaccess::L1RSMEND
volatile uint16_t L1RSMEND
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_ccrx_evenaccess::DVSE
volatile uint16_t DVSE
Definition: rusb2_type.h:325
_ccrx_evenaccess::PHYTRIM2
volatile uint16_t PHYTRIM2
Definition: rusb2_type.h:901
_ccrx_evenaccess::SLEWR00
volatile uint32_t SLEWR00
Definition: rusb2_type.h:787
_ccrx_evenaccess::IDPSRCE
volatile uint16_t IDPSRCE
Definition: rusb2_type.h:821
_ccrx_evenaccess::PIPE4BRDY
volatile uint16_t PIPE4BRDY
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_ccrx_evenaccess::DOVCBH
volatile const uint32_t DOVCBH
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volatile const uint16_t PDDETSTS
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_ccrx_evenaccess::CFIFOLL
volatile uint8_t CFIFOLL
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_ccrx_evenaccess::TRENB
uint16_t TRENB
Definition: rusb2_type.h:58
_ccrx_evenaccess::L1ADDR
volatile uint16_t L1ADDR
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_ccrx_evenaccess::PIPE9BRDYE
volatile uint16_t PIPE9BRDYE
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_ccrx_evenaccess::BRDYENB
volatile uint16_t BRDYENB
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RUSB2_PIPE_TR_t::N
volatile uint16_t N
Definition: rusb2_type.h:79
RUSB2_PIPE_TR_t::E
volatile uint16_t E
Definition: rusb2_type.h:68
RUSB2_PIPE_TR_t::TRNCNT
volatile uint16_t TRNCNT
Definition: rusb2_type.h:82
RUSB2_PIPE_TR_t::TRENB
volatile uint16_t TRENB
Definition: rusb2_type.h:73
RUSB2_PIPE_TR_t::TRCLR
volatile uint16_t TRCLR
Definition: rusb2_type.h:72
TU_ATTR_PACKED
AUDIO Channel Cluster Descriptor (4.1)
Definition: audio.h:647
TU_ATTR_PACKED::uint16_t
volatile uint16_t
Definition: hcd_rusb2.c:58