Open FFBoard
Open source force feedback firmware
dwc2_type.h
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1/*
2 * The MIT License (MIT)
3 *
4 * Copyright (c) 2024, hathach (tinyusb.org)
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 *
24 */
34#ifndef TUSB_DWC2_TYPES_H_
35#define TUSB_DWC2_TYPES_H_
36
37#include "stdint.h"
38
39#ifdef __cplusplus
40 extern "C" {
41#endif
42
43// Controller
44typedef struct
45{
46 uintptr_t reg_base;
47 uint32_t irqnum;
48 uint8_t ep_count;
49 uint8_t ep_in_count;
50 uint32_t ep_fifo_size;
51}dwc2_controller_t;
52
53// DWC OTG HW Release versions
54#define DWC2_CORE_REV_2_71a 0x4f54271a
55#define DWC2_CORE_REV_2_72a 0x4f54272a
56#define DWC2_CORE_REV_2_80a 0x4f54280a
57#define DWC2_CORE_REV_2_90a 0x4f54290a
58#define DWC2_CORE_REV_2_91a 0x4f54291a
59#define DWC2_CORE_REV_2_92a 0x4f54292a
60#define DWC2_CORE_REV_2_94a 0x4f54294a
61#define DWC2_CORE_REV_3_00a 0x4f54300a
62#define DWC2_CORE_REV_3_10a 0x4f54310a
63#define DWC2_CORE_REV_4_00a 0x4f54400a
64#define DWC2_CORE_REV_4_11a 0x4f54411a
65#define DWC2_CORE_REV_4_20a 0x4f54420a
66#define DWC2_FS_IOT_REV_1_00a 0x5531100a
67#define DWC2_HS_IOT_REV_1_00a 0x5532100a
68#define DWC2_CORE_REV_MASK 0x0000ffff
69
70// DWC OTG HW Core ID
71#define DWC2_OTG_ID 0x4f540000
72#define DWC2_FS_IOT_ID 0x55310000
73#define DWC2_HS_IOT_ID 0x55320000
74
75#if 0
76// HS PHY
77typedef struct
78{
79 volatile uint32_t HS_PHYC_PLL; // 000h This register is used to control the PLL of the HS PHY.
80 volatile uint32_t Reserved04; // 004h Reserved
81 volatile uint32_t Reserved08; // 008h Reserved
82 volatile uint32_t HS_PHYC_TUNE; // 00Ch This register is used to control the tuning interface of the High Speed PHY.
83 volatile uint32_t Reserved10; // 010h Reserved
84 volatile uint32_t Reserved14; // 014h Reserved
85 volatile uint32_t HS_PHYC_LDO; // 018h This register is used to control the regulator (LDO).
86} HS_PHYC_GlobalTypeDef;
87#endif
88
89enum {
90 GOTGCTL_OTG_VERSION_1_3 = 0,
91 GOTGCTL_OTG_VERSION_2_0 = 1,
92};
93
94enum {
95 GHWCFG2_OPMODE_HNP_SRP = 0,
96 GHWCFG2_OPMODE_SRP = 1,
97 GHWCFG2_OPMODE_NON_HNP_NON_SRP = 2,
98 GHWCFG2_OPMODE_SRP_DEVICE = 3,
99 GHWCFFG2_OPMODE_NON_OTG_DEVICE = 4,
100 GHWCFG2_OPMODE_SRP_HOST = 5,
101 GHWCFG2_OPMODE_NON_OTG_HOST = 6,
102};
103enum {
104 GHWCFG2_ARCH_SLAVE_ONLY = 0,
105 GHWCFG2_ARCH_EXTERNAL_DMA = 1,
106 GHWCFG2_ARCH_INTERNAL_DMA = 2,
107};
108
109enum {
110 GHWCFG2_HSPHY_NOT_SUPPORTED = 0,
111 GHWCFG2_HSPHY_UTMI = 1, // internal PHY (mostly)
112 GHWCFG2_HSPHY_ULPI = 2, // external PHY (mostly)
113 GHWCFG2_HSPHY_UTMI_ULPI = 3, // both
114
115};
116
117enum {
118 GHWCFG2_FSPHY_NOT_SUPPORTED = 0,
119 GHWCFG2_FSPHY_DEDICATED = 1, // have dedicated FS PHY
120 GHWCFG2_FSPHY_UTMI = 2, // shared with UTMI+
121 GHWCFG2_FSPHY_ULPI = 3, // shared with ULPI
122};
123
124enum {
125 GHWCFFG4_PHY_DATA_WIDTH_8 = 0,
126 GHWCFFG4_PHY_DATA_WIDTH_16 = 1,
127 GHWCFFG4_PHY_DATA_WIDTH_8_16 = 2, // software selectable
128};
129
130enum {
131 HPRT_SPEED_HIGH = 0,
132 HPRT_SPEED_FULL = 1,
133 HPRT_SPEED_LOW = 2
134};
135
136enum {
137 GINTSTS_CMODE_DEVICE = 0,
138 GINTSTS_CMODE_HOST = 1,
139};
140
141enum {
142 HCTSIZ_PID_DATA0 = 0, // 00b
143 HCTSIZ_PID_DATA2 = 1, // 01b
144 HCTSIZ_PID_DATA1 = 2, // 10b
145 HCTSIZ_PID_SETUP = 3, // 11b
146};
147enum {
148 HCTSIZ_PID_MDATA = 3,
149};
150
151enum {
152 GRXSTS_PKTSTS_GLOBALOUTNAK = 1,
153 GRXSTS_PKTSTS_OUTRX = 2,
154 GRXSTS_PKTSTS_OUTDONE = 3,
155 GRXSTS_PKTSTS_SETUPDONE = 4,
156 GRXSTS_PKTSTS_SETUPRX = 6
157};
158
159enum {
160 GRXSTS_PKTSTS_RX_DATA = 2,
161 GRXSTS_PKTSTS_RX_COMPLETE = 3,
162 GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR = 5,
163 GRXSTS_PKTSTS_HOST_CHANNEL_HALTED = 7
164};
165
166// Same as TUSB_XFER_*
167enum {
168 HCCHAR_EPTYPE_CONTROL = 0,
169 HCCHAR_EPTYPE_ISOCHRONOUS = 1,
170 HCCHAR_EPTYPE_BULK = 2,
171 HCCHAR_EPTYPE_INTERRUPT = 3
172};
173
174//--------------------------------------------------------------------
175// Common Register Bitfield
176//--------------------------------------------------------------------
177typedef struct TU_ATTR_PACKED {
178 uint32_t ses_req_scs : 1; // 0 Session request success
179 uint32_t ses_req : 1; // 1 Session request
180 uint32_t vbval_ov_en : 1; // 2 VBUS valid override enable
181 uint32_t vbval_ov_val : 1; // 3 VBUS valid override value
182 uint32_t aval_ov_en : 1; // 4 A-peripheral session valid override enable
183 uint32_t aval_ov_al : 1; // 5 A-peripheral session valid override value
184 uint32_t bval_ov_en : 1; // 6 B-peripheral session valid override enable
185 uint32_t bval_ov_val : 1; // 7 B-peripheral session valid override value
186 uint32_t hng_scs : 1; // 8 Host negotiation success
187 uint32_t hnp_rq : 1; // 9 HNP (host negotiation protocol) request
188 uint32_t host_set_hnp_en : 1; // 10 Host set HNP enable
189 uint32_t dev_hnp_en : 1; // 11 Device HNP enabled
190 uint32_t embedded_host_en : 1; // 12 Embedded host enable
191 uint32_t rsv13_14 : 2; // 13.14 Reserved
192 uint32_t dbnc_filter_bypass : 1; // 15 Debounce filter bypass
193 uint32_t cid_status : 1; // 16 Connector ID status
194 uint32_t dbnc_done : 1; // 17 Debounce done
195 uint32_t ases_valid : 1; // 18 A-session valid
196 uint32_t bses_valid : 1; // 19 B-session valid
197 uint32_t otg_ver : 1; // 20 OTG version 0: v1.3, 1: v2.0
198 uint32_t current_mode : 1; // 21 Current mode of operation. Only from v3.00a
199 uint32_t mult_val_id_bc : 5; // 22..26 Multi-valued input pin ID battery charger
200 uint32_t chirp_en : 1; // 27 Chirp detection enable
201 uint32_t rsv28_30 : 3; // 28.30: Reserved
202 uint32_t test_mode_corr_eusb2 : 1; // 31 Test mode control for eUSB2 PHY
203} dwc2_gotgctl_t;
204TU_VERIFY_STATIC(sizeof(dwc2_gotgctl_t) == 4, "incorrect size");
205
206typedef struct TU_ATTR_PACKED {
207 uint32_t rsv0_1 : 2; // 0..1 Reserved
208 uint32_t ses_end_det : 1; // 2 Session end detected
209 uint32_t rsv3_7 : 5; // 3..7 Reserved
210 uint32_t srs_status_change : 1; // 8 Session request success status change
211 uint32_t hns_status_change : 1; // 9 Host negotiation success status change
212 uint32_t rsv10_16 : 7; // 10..16 Reserved
213 uint32_t hng_det : 1; // 17 Host negotiation detected
214 uint32_t adev_timeout_change : 1; // 18 A-device timeout change
215 uint32_t dbnc_done : 1; // 19 Debounce done
216 uint32_t mult_val_lp_change : 1; // 20 Multi-valued input pin change
217 uint32_t rsv21_31 :11; // 21..31 Reserved
218} dwc2_gotgint_t;
219TU_VERIFY_STATIC(sizeof(dwc2_gotgint_t) == 4, "incorrect size");
220
221typedef struct TU_ATTR_PACKED {
222 uint32_t gintmask : 1; // 0 Global interrupt mask
223 uint32_t hbst_len : 4; // 1..4 Burst length/type
224 uint32_t dma_en : 1; // 5 DMA enable
225 uint32_t rsv6 : 1; // 6 Reserved
226 uint32_t nptxf_empty_lvl : 1; // 7 Non-periodic Tx FIFO empty level
227 uint32_t ptxf_empty_lvl : 1; // 8 Periodic Tx FIFO empty level
228 uint32_t rsv9_20 : 12; // 9.20: Reserved
229 uint32_t remote_mem_support : 1; // 21 Remote memory support
230 uint32_t notify_all_dma_write : 1; // 22 Notify all DMA writes
231 uint32_t ahb_single : 1; // 23 AHB single
232 uint32_t inv_desc_endian : 1; // 24 Inverse descriptor endian
233 uint32_t rsv25_31 : 7; // 25..31 Reserved
234} dwc2_gahbcfg_t;
235TU_VERIFY_STATIC(sizeof(dwc2_gahbcfg_t) == 4, "incorrect size");
236
237typedef struct TU_ATTR_PACKED {
238 uint32_t timeout_cal : 3; /* 0..2 Timeout calibration.
239 The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard
240 timeout value for full- speed operation is 16 to 18 (inclusive) bit times. The application must program this field
241 based on the speed of enumeration. The number of bit times added per PHY clock are as follows:
242 - High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times
243 - Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */
244 uint32_t phy_if16 : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits
245 uint32_t ulpi_utmi_sel : 1; // 4 ULPI/UTMI select. 0: UTMI+, 1: ULPI
246 uint32_t fs_intf_sel : 1; // 5 Fullspeed serial interface select. 0: 6-pin, 1: 3-pin
247 uint32_t phy_sel : 1; // 6 HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver
248 uint32_t ddr_sel : 1; // 7 ULPI DDR select. 0: Single data rate 8-bit, 1: Double data rate 4-bit
249 uint32_t srp_capable : 1; // 8 SRP-capable
250 uint32_t hnp_capable : 1; // 9 HNP-capable
251 uint32_t turnaround_time : 4; // 10..13 Turnaround time. 9: 8-bit UTMI+, 5: 16-bit UTMI+
252 uint32_t rsv14 : 1; // 14 Reserved
253 uint32_t phy_low_power_clk_sel : 1; /* 15 PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode.
254 In FS/LS modes, the PHY can usually operate on a 48-MHz clock to save power. This bit is valid only for UTMI+ PHYs.
255 - 0: 480 Mhz internal PLL: the UTMI interface operates at either 60 MHz (8 bit) or 30 MHz (16-bit)
256 - 1 48 Mhz external clock: the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode */
257 uint32_t otg_i2c_sel : 1; // 16 OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals
258 uint32_t ulpi_fsls : 1; /* 17 ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS.
259 valid only when the FS serial transceiver is selected on the ULPI PHY. */
260 uint32_t ulpi_auto_resume : 1; // 18 ULPI Auto-resume
261 uint32_t ulpi_clk_sus_m : 1; // 19 ULPI Clock SuspendM
262 uint32_t ulpi_ext_vbus_drv : 1; // 20 ULPI External VBUS Drive
263 uint32_t ulpi_int_vbus_indicator : 1; // 21 ULPI Internal VBUS Indicator
264 uint32_t term_sel_dl_pulse : 1; // 22 TermSel DLine pulsing
265 uint32_t indicator_complement : 1; // 23 Indicator complement
266 uint32_t indicator_pass_through : 1; // 24 Indicator pass through
267 uint32_t ulpi_if_protect_disable : 1; // 25 ULPI interface protect disable
268 uint32_t ic_usb_capable : 1; // 26 IC_USB Capable
269 uint32_t ic_usb_traf_ctl : 1; // 27 IC_USB Traffic Control
270 uint32_t tx_end_delay : 1; // 28 TX end delay
271 uint32_t force_host_mode : 1; // 29 Force host mode
272 uint32_t force_dev_mode : 1; // 30 Force device mode
273 uint32_t corrupt_tx_pkt : 1; // 31 Corrupt Tx packet. 0: normal, 1: debug
274} dwc2_gusbcfg_t;
275TU_VERIFY_STATIC(sizeof(dwc2_gusbcfg_t) == 4, "incorrect size");
276
277typedef struct TU_ATTR_PACKED {
278 uint32_t core_soft_rst : 1; // 0 Core Soft Reset
279 uint32_t piufs_soft_rst : 1; // 1 PIU FS Dedicated Controller Soft Reset
280 uint32_t frame_counter_rst : 1; // 2 Frame Counter Reset (host)
281 uint32_t intoken_q_flush : 1; // 3 IN Token Queue Flush
282 uint32_t rx_fifo_flush : 1; // 4 RX FIFO Flush
283 uint32_t tx_fifo_flush : 1; // 5 TX FIFO Flush
284 uint32_t tx_fifo_num : 5; // 6..10 TX FIFO Number
285 uint32_t rsv11_28 :18; // 11..28 Reserved
286 uint32_t core_soft_rst_done : 1; // 29 Core Soft Reset Done, from v4.20a
287 uint32_t dma_req : 1; // 30 DMA Request
288 uint32_t ahb_idle : 1; // 31 AHB Idle
289} dwc2_grstctl_t;
290TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size");
291
292typedef struct TU_ATTR_PACKED {
293 uint32_t ep_ch_num : 4; // 0..3 Endpoint/Channel Number
294 uint32_t byte_count :11; // 4..14 Byte Count
295 uint32_t dpid : 2; // 15..16 Data PID
296 uint32_t packet_status : 4; // 17..20 Packet Status
297 uint32_t frame_number : 4; // 21..24 Frame Number
298 uint32_t rsv25_31 : 7; // 25..31 Reserved
299} dwc2_grxstsp_t;
300TU_VERIFY_STATIC(sizeof(dwc2_grxstsp_t) == 4, "incorrect size");
301
302// Hardware Configuration
303typedef struct TU_ATTR_PACKED {
304 uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode
305 uint32_t arch : 2; // 3..4 Slave/External/Internal DMA
306 uint32_t single_point : 1; // 5 0: support hub and split | 1: no hub, no split
307 uint32_t hs_phy_type : 2; // 6..7 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
308 uint32_t fs_phy_type : 2; // 8..9 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
309 uint32_t num_dev_ep : 4; // 10..13 Number of device endpoints (excluding EP0)
310 uint32_t num_host_ch : 4; // 14..17 Number of host channel (excluding control)
311 uint32_t period_channel_support : 1; // 18 Support Periodic OUT Host Channel
312 uint32_t enable_dynamic_fifo : 1; // 19 Dynamic FIFO Sizing Enabled
313 uint32_t mul_proc_intrpt : 1; // 20 Multi-Processor Interrupt enabled (OTG_MULTI_PROC_INTRPT)
314 uint32_t reserved21 : 1; // 21 reserved
315 uint32_t nptx_q_depth : 2; // 22..23 Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
316 uint32_t ptx_q_depth : 2; // 24..25 Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
317 uint32_t token_q_depth : 5; // 26..30 Device IN token sequence learning queue depth: 0-30
318 uint32_t otg_enable_ic_usb : 1; // 31 IC_USB mode specified for mode of operation
319} dwc2_ghwcfg2_t;
320TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size");
321
322typedef struct TU_ATTR_PACKED {
323 uint32_t xfer_size_width : 4; // 0..3 Transfer size counter in bits = 11 + n (max 19 bits)
324 uint32_t packet_size_width : 3; // 4..6 Packet size counter in bits = 4 + n (max 10 bits)
325 uint32_t otg_enable : 1; // 7 OTG capable
326 uint32_t i2c_enable : 1; // 8 I2C interface is available
327 uint32_t vendor_ctrl_itf : 1; // 9 Vendor control interface is available
328 uint32_t optional_feature_removed : 1; // 10 remove User ID, GPIO, SOF toggle & counter to save gate count
329 uint32_t synch_reset : 1; // 11 0: async reset | 1: synch reset
330 uint32_t otg_adp_support : 1; // 12 ADP logic is present along with HSOTG controller
331 uint32_t otg_enable_hsic : 1; // 13 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
332 uint32_t battery_charger_support : 1; // s14 upport battery charger
333 uint32_t lpm_mode : 1; // 15 LPM mode
334 uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words
335}dwc2_ghwcfg3_t;
336TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size");
337
338typedef struct TU_ATTR_PACKED {
339 uint32_t num_dev_period_in_ep : 4; // 0..3 Number of Device Periodic IN Endpoints
340 uint32_t partial_powerdown : 1; // 4 Partial Power Down Enabled
341 uint32_t ahb_freq_min : 1; // 5 1: minimum of AHB frequency is less than 60 MHz
342 uint32_t hibernation : 1; // 6 Hibernation feature is enabled
343 uint32_t extended_hibernation : 1; // 7 Extended Hibernation feature is enabled
344 uint32_t reserved8 : 1; // 8 Reserved
345 uint32_t enhanced_lpm_support1 : 1; // 9 Enhanced LPM Support1
346 uint32_t service_interval_flow : 1; // 10 Service Interval flow is supported
347 uint32_t ipg_isoc_support : 1; // 11 Interpacket GAP ISO OUT worst-case is supported
348 uint32_t acg_support : 1; // 12 Active clock gating is supported
349 uint32_t enhanced_lpm_support : 1; // 13 Enhanced LPM Support
350 uint32_t phy_data_width : 2; // 14..15 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
351 uint32_t ctrl_ep_num : 4; // 16..19 Number of Device control endpoints in addition to EP0
352 uint32_t iddg_filter : 1; // 20 IDDG Filter Enabled
353 uint32_t vbus_valid_filter : 1; // 21 VBUS Valid Filter Enabled
354 uint32_t a_valid_filter : 1; // 22 A Valid Filter Enabled
355 uint32_t b_valid_filter : 1; // 23 B Valid Filter Enabled
356 uint32_t session_end_filter : 1; // 24 Session End Filter Enabled
357 uint32_t dedicated_fifos : 1; // 25 Dedicated tx fifo for device IN Endpoint
358 uint32_t num_dev_in_eps : 4; // 26..29 Number of Device IN Endpoints including EP0
359 uint32_t dma_desc_enabled : 1; // scatter/gather DMA configuration enabled
360 uint32_t dma_desc_dynamic : 1; // Dynamic scatter/gather DMA
361}dwc2_ghwcfg4_t;
362TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size");
363
364//--------------------------------------------------------------------
365// Host Register Bitfield
366//--------------------------------------------------------------------
367
368typedef struct TU_ATTR_PACKED {
369 uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO
370 uint32_t req_queue_available : 8; // 16..23 Number of spaces available in the NPT transmit request queue for both IN and OU
371 // 24..31 is top entry in the request queue that is currently being processed by the MAC
372 uint32_t qtop_terminate : 1; // 24 Last entry for selected channel
373 uint32_t qtop_type : 2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command
374 uint32_t qtop_ch_num : 4; // 27..30 Channel number
375} dwc2_hnptxsts_t;
376TU_VERIFY_STATIC(sizeof(dwc2_hnptxsts_t) == 4, "incorrect size");
377
378typedef struct TU_ATTR_PACKED {
379 uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO
380 uint32_t req_queue_available : 7; // 16..22 Number of spaces available in the PTX transmit request queue
381 uint32_t qtop_terminate : 1; // 23 Last entry for selected channel
382 uint32_t qtop_last_period : 1; // 24 Last entry for selected channel is a periodic entry
383 uint32_t qtop_type : 2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command
384 uint32_t qtop_ch_num : 4; // 27..30 Channel number
385 uint32_t qtop_odd_frame : 1; // 31 Send in odd frame
386} dwc2_hptxsts_t;
387TU_VERIFY_STATIC(sizeof(dwc2_hptxsts_t) == 4, "incorrect size");
388
389typedef struct TU_ATTR_PACKED {
390 uint32_t conn_status : 1; // 0 Port connect status
391 uint32_t conn_detected : 1; // 1 Port connect detected
392 uint32_t enable : 1; // 2 Port enable status
393 uint32_t enable_change : 1; // 3 Port enable change
394 uint32_t over_current_active : 1; // 4 Port Over-current active
395 uint32_t over_current_change : 1; // 5 Port Over-current change
396 uint32_t resume : 1; // 6 Port resume
397 uint32_t suspend : 1; // 7 Port suspend
398 uint32_t reset : 1; // 8 Port reset
399 uint32_t rsv9 : 1; // 9 Reserved
400 uint32_t line_status : 2; // 10..11 Line status
401 uint32_t power : 1; // 12 Port power
402 uint32_t test_control : 4; // 13..16 Port Test control
403 uint32_t speed : 2; // 17..18 Port speed
404 uint32_t rsv19_31 :13; // 19..31 Reserved
405}dwc2_hprt_t;
406TU_VERIFY_STATIC(sizeof(dwc2_hprt_t) == 4, "incorrect size");
407
408typedef struct TU_ATTR_PACKED {
409 uint32_t ep_size : 11; // 0..10 Maximum packet size
410 uint32_t ep_num : 4; // 11..14 Endpoint number
411 uint32_t ep_dir : 1; // 15 Endpoint direction
412 uint32_t rsv16 : 1; // 16 Reserved
413 uint32_t low_speed_dev : 1; // 17 Low-speed device
414 uint32_t ep_type : 2; // 18..19 Endpoint type
415 uint32_t err_multi_count : 2; // 20..21 Error (splitEn = 1) / Multi (SplitEn = 0) count
416 uint32_t dev_addr : 7; // 22..28 Device address
417 uint32_t odd_frame : 1; // 29 Odd frame
418 uint32_t disable : 1; // 30 Channel disable
419 uint32_t enable : 1; // 31 Channel enable
420} dwc2_channel_char_t;
421TU_VERIFY_STATIC(sizeof(dwc2_channel_char_t) == 4, "incorrect size");
422
423typedef struct TU_ATTR_PACKED {
424 uint32_t hub_port : 7; // 0..6 Hub port number
425 uint32_t hub_addr : 7; // 7..13 Hub address
426 uint32_t xact_pos : 2; // 14..15 Transaction position
427 uint32_t split_compl : 1; // 16 Split completion
428 uint32_t rsv17_30 : 14; // 17..30 Reserved
429 uint32_t split_en : 1; // 31 Split enable
430} dwc2_channel_split_t;
431TU_VERIFY_STATIC(sizeof(dwc2_channel_split_t) == 4, "incorrect size");
432
433typedef struct TU_ATTR_PACKED {
434 uint32_t xfer_size : 19; // 0..18 Transfer size in bytes
435 uint32_t packet_count : 10; // 19..28 Number of packets
436 uint32_t pid : 2; // 29..30 Packet ID
437 uint32_t do_ping : 1; // 31 Do PING
438} dwc2_channel_tsize_t;
439TU_VERIFY_STATIC(sizeof(dwc2_channel_tsize_t) == 4, "incorrect size");
440
441typedef struct TU_ATTR_PACKED {
442 uint32_t num : 16; // 0..15 Frame number
443 uint32_t remainning : 16; // 16..31 Frame remaining
444} dwc2_hfnum_t;
445TU_VERIFY_STATIC(sizeof(dwc2_hfnum_t) == 4, "incorrect size");
446
447// Host Channel
448typedef struct {
449 union {
450 volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics
451 volatile dwc2_channel_char_t hcchar_bm;
452 };
453 union {
454 volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control
455 volatile dwc2_channel_split_t hcsplt_bm;
456 };
457 volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt
458 volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask
459 union {
460 volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size
461 volatile dwc2_channel_tsize_t hctsiz_bm;
462 };
463 volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address
464 uint32_t reserved518; // 518 + 20*ch
465 volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address
466} dwc2_channel_t;
467
468//--------------------------------------------------------------------
469// Device Register Bitfield
470//--------------------------------------------------------------------
471typedef struct TU_ATTR_PACKED {
472 uint32_t xfer_size : 19; // 0..18 Transfer size in bytes
473 uint32_t packet_count : 10; // 19..28 Number of packets
474 uint32_t mc_pid : 2; // 29..30 IN: Multi Count, OUT: PID
475} dwc2_ep_tsize_t;
476TU_VERIFY_STATIC(sizeof(dwc2_ep_tsize_t) == 4, "incorrect size");
477
478// Endpoint IN
479typedef struct {
480 volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control
481 uint32_t reserved04; // 904
482 volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt
483 uint32_t reserved0c; // 90C
484 union {
485 volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size
486 volatile dwc2_ep_tsize_t dieptsiz_bm;
487 };
488 volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address
489 volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status
490 uint32_t reserved1c; // 91C
491} dwc2_epin_t;
492
493// Endpoint OUT
494typedef struct {
495 volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control
496 uint32_t reserved04; // B04
497 volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt
498 uint32_t reserved0c; // B0C
499 union {
500 volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size
501 volatile dwc2_ep_tsize_t doeptsiz_bm;
502 };
503 volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address
504 uint32_t reserved18[2]; // B18..B1C
505} dwc2_epout_t;
506
507// Universal Endpoint
508typedef struct {
509 union {
510 volatile uint32_t diepctl;
511 volatile uint32_t doepctl;
512 volatile uint32_t ctl;
513 };
514 uint32_t rsv04;
515 union {
516 volatile uint32_t diepint;
517 volatile uint32_t doepint;
518 };
519 uint32_t rsv0c;
520 union {
521 volatile uint32_t dieptsiz;
522 volatile uint32_t doeptsiz;
523 volatile dwc2_ep_tsize_t deptsiz_bm;
524 };
525 union {
526 volatile uint32_t diepdma;
527 volatile uint32_t doepdma;
528 };
529 volatile uint32_t dtxfsts;
530 uint32_t rsv1c;
531}dwc2_dep_t;
532
533TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size");
534
535//--------------------------------------------------------------------
536// CSR Register Map
537//--------------------------------------------------------------------
538typedef struct {
539 //------------- Core Global -------------//
540 union {
541 volatile uint32_t gotgctl; // 000 OTG Control and Status
542 volatile dwc2_gotgctl_t gotgctl_bm;
543 };
544 union {
545 volatile uint32_t gotgint; // 004 OTG Interrupt
546 volatile dwc2_gotgint_t gotgint_bm;
547 };
548 union {
549 volatile uint32_t gahbcfg; // 008 AHB Configuration
550 volatile dwc2_gahbcfg_t gahbcfg_bm;
551 };
552 union {
553 volatile uint32_t gusbcfg; // 00c USB Configuration
554 volatile dwc2_gusbcfg_t gusbcfg_bm;
555 };
556 union {
557 volatile uint32_t grstctl; // 010 Reset
558 volatile dwc2_grstctl_t grstctl_bm;
559 };
560 volatile uint32_t gintsts; // 014 Interrupt
561 volatile uint32_t gintmsk; // 018 Interrupt Mask
562 volatile uint32_t grxstsr; // 01c Receive Status Debug Read
563 union {
564 volatile uint32_t grxstsp; // 020 Receive Status Read/Pop
565 volatile dwc2_grxstsp_t grxstsp_bm;
566 };
567 volatile uint32_t grxfsiz; // 024 Receive FIFO Size
568 union {
569 volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size
570 volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size
571 };
572 union {
573 volatile uint32_t hnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status
574 volatile dwc2_hnptxsts_t hnptxsts_bm;
575 volatile uint32_t gnptxsts;
576 };
577 volatile uint32_t gi2cctl; // 030 I2C Address
578 volatile uint32_t gpvndctl; // 034 PHY Vendor Control
579 union {
580 volatile uint32_t ggpio; // 038 General Purpose IO
581 volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration
582 };
583 volatile uint32_t guid; // 03C User (Application programmable) ID
584 volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version
585 volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
586 union {
587 volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2
588 volatile dwc2_ghwcfg2_t ghwcfg2_bm;
589 };
590 union {
591 volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3
592 volatile dwc2_ghwcfg3_t ghwcfg3_bm;
593 };
594 union {
595 volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4
596 volatile dwc2_ghwcfg4_t ghwcfg4_bm;
597 };
598 volatile uint32_t glpmcfg; // 054 Core LPM Configuration
599 volatile uint32_t gpwrdn; // 058 Power Down
600 volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration
601 volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status
602 uint32_t reserved64[39]; // 064..0FF
603 volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size
604 volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size
605 uint32_t reserved140[176]; // 140..3FF
606
607 //------------ Host -------------//
608 volatile uint32_t hcfg; // 400 Host Configuration
609 volatile uint32_t hfir; // 404 Host Frame Interval
610 union {
611 volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining
612 volatile dwc2_hfnum_t hfnum_bm;
613 };
614 uint32_t reserved40c; // 40C
615 union {
616 volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status
617 volatile dwc2_hptxsts_t hptxsts_bm;
618 };
619 volatile uint32_t haint; // 414 Host All Channels Interrupt
620 volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask
621 volatile uint32_t hflbaddr; // 41C Host Frame List Base Address
622 uint32_t reserved420[8]; // 420..43F
623 union {
624 volatile uint32_t hprt; // 440 Host Port Control and Status
625 volatile dwc2_hprt_t hprt_bm;
626 };
627 uint32_t reserved444[47]; // 444..4FF
628
629 //------------- Host Channel -------------//
630 dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15
631 uint32_t reserved700[64]; // 700..7FF
632
633 //------------- Device -----------//
634 volatile uint32_t dcfg; // 800 Device Configuration
635 volatile uint32_t dctl; // 804 Device Control
636 volatile uint32_t dsts; // 808 Device Status (RO)
637 uint32_t reserved80c; // 80C
638 volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask
639 volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask
640 volatile uint32_t daint; // 818 Device All Endpoints Interrupt
641 volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask
642 volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1
643 volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2
644 volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time
645 volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time
646 volatile uint32_t dthrctl; // 830 Device threshold Control
647 volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask
648
649 // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line
650 // require OTG_MULTI_PROC_INTRPT=1
651 volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt
652 volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt mask
653 volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask
654 volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask
655 uint32_t reserved8c0[16]; // 8C0..8FF
656
657 //------------- Device Endpoint -------------//
658 union {
659 dwc2_dep_t ep[2][16]; // 0: IN, 1 OUT
660 struct {
661 dwc2_epin_t epin[16]; // 900..AFF IN Endpoints
662 dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints
663 };
664 };
665 uint32_t reservedd00[64]; // D00..DFF
666
667 //------------- Power Clock -------------//
668 volatile uint32_t pcgcctl; // E00 Power and Clock Gating Characteristic Control
669 volatile uint32_t pcgcctl1; // E04 Power and Clock Gating Characteristic Control 1
670 uint32_t reservede08[126]; // E08..FFF
671
672 //------------- FIFOs -------------//
673 // Word-accessed only using first pointer since it auto shift
674 volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO
675} dwc2_regs_t;
676
677TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size");
678TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size");
679TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size");
680TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin ) == 0x0900, "incorrect size");
681TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0x0B00, "incorrect size");
682TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgcctl) == 0x0E00, "incorrect size");
683TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
684
685//--------------------------------------------------------------------+
686// Register Bit Definitions
687//--------------------------------------------------------------------+
688
689/******************** Bit definition for GOTGCTL register ********************/
690#define GOTGCTL_SRQSCS_Pos (0U)
691#define GOTGCTL_SRQSCS_Msk (0x1UL << GOTGCTL_SRQSCS_Pos) // 0x00000001
692#define GOTGCTL_SRQSCS GOTGCTL_SRQSCS_Msk // Session request success
693#define GOTGCTL_SRQ_Pos (1U)
694#define GOTGCTL_SRQ_Msk (0x1UL << GOTGCTL_SRQ_Pos) // 0x00000002
695#define GOTGCTL_SRQ GOTGCTL_SRQ_Msk // Session request
696#define GOTGCTL_VBVALOEN_Pos (2U)
697#define GOTGCTL_VBVALOEN_Msk (0x1UL << GOTGCTL_VBVALOEN_Pos) // 0x00000004
698#define GOTGCTL_VBVALOEN GOTGCTL_VBVALOEN_Msk // VBUS valid override enable
699#define GOTGCTL_VBVALOVAL_Pos (3U)
700#define GOTGCTL_VBVALOVAL_Msk (0x1UL << GOTGCTL_VBVALOVAL_Pos) // 0x00000008
701#define GOTGCTL_VBVALOVAL GOTGCTL_VBVALOVAL_Msk // VBUS valid override value
702#define GOTGCTL_AVALOEN_Pos (4U)
703#define GOTGCTL_AVALOEN_Msk (0x1UL << GOTGCTL_AVALOEN_Pos) // 0x00000010
704#define GOTGCTL_AVALOEN GOTGCTL_AVALOEN_Msk // A-peripheral session valid override enable
705#define GOTGCTL_AVALOVAL_Pos (5U)
706#define GOTGCTL_AVALOVAL_Msk (0x1UL << GOTGCTL_AVALOVAL_Pos) // 0x00000020
707#define GOTGCTL_AVALOVAL GOTGCTL_AVALOVAL_Msk // A-peripheral session valid override value
708#define GOTGCTL_BVALOEN_Pos (6U)
709#define GOTGCTL_BVALOEN_Msk (0x1UL << GOTGCTL_BVALOEN_Pos) // 0x00000040
710#define GOTGCTL_BVALOEN GOTGCTL_BVALOEN_Msk // B-peripheral session valid override enable
711#define GOTGCTL_BVALOVAL_Pos (7U)
712#define GOTGCTL_BVALOVAL_Msk (0x1UL << GOTGCTL_BVALOVAL_Pos) // 0x00000080
713#define GOTGCTL_BVALOVAL GOTGCTL_BVALOVAL_Msk // B-peripheral session valid override value
714#define GOTGCTL_HNGSCS_Pos (8U)
715#define GOTGCTL_HNGSCS_Msk (0x1UL << GOTGCTL_HNGSCS_Pos) // 0x00000100
716#define GOTGCTL_HNGSCS GOTGCTL_HNGSCS_Msk // Host set HNP enable
717#define GOTGCTL_HNPRQ_Pos (9U)
718#define GOTGCTL_HNPRQ_Msk (0x1UL << GOTGCTL_HNPRQ_Pos) // 0x00000200
719#define GOTGCTL_HNPRQ GOTGCTL_HNPRQ_Msk // HNP request
720#define GOTGCTL_HSHNPEN_Pos (10U)
721#define GOTGCTL_HSHNPEN_Msk (0x1UL << GOTGCTL_HSHNPEN_Pos) // 0x00000400
722#define GOTGCTL_HSHNPEN GOTGCTL_HSHNPEN_Msk // Host set HNP enable
723#define GOTGCTL_DHNPEN_Pos (11U)
724#define GOTGCTL_DHNPEN_Msk (0x1UL << GOTGCTL_DHNPEN_Pos) // 0x00000800
725#define GOTGCTL_DHNPEN GOTGCTL_DHNPEN_Msk // Device HNP enabled
726#define GOTGCTL_EHEN_Pos (12U)
727#define GOTGCTL_EHEN_Msk (0x1UL << GOTGCTL_EHEN_Pos) // 0x00001000
728#define GOTGCTL_EHEN GOTGCTL_EHEN_Msk // Embedded host enable
729#define GOTGCTL_CIDSTS_Pos (16U)
730#define GOTGCTL_CIDSTS_Msk (0x1UL << GOTGCTL_CIDSTS_Pos) // 0x00010000
731#define GOTGCTL_CIDSTS GOTGCTL_CIDSTS_Msk // Connector ID status
732#define GOTGCTL_DBCT_Pos (17U)
733#define GOTGCTL_DBCT_Msk (0x1UL << GOTGCTL_DBCT_Pos) // 0x00020000
734#define GOTGCTL_DBCT GOTGCTL_DBCT_Msk // Long/short debounce time
735#define GOTGCTL_ASVLD_Pos (18U)
736#define GOTGCTL_ASVLD_Msk (0x1UL << GOTGCTL_ASVLD_Pos) // 0x00040000
737#define GOTGCTL_ASVLD GOTGCTL_ASVLD_Msk // A-session valid
738#define GOTGCTL_BSESVLD_Pos (19U)
739#define GOTGCTL_BSESVLD_Msk (0x1UL << GOTGCTL_BSESVLD_Pos) // 0x00080000
740#define GOTGCTL_BSESVLD GOTGCTL_BSESVLD_Msk // B-session valid
741#define GOTGCTL_OTGVER_Pos (20U)
742#define GOTGCTL_OTGVER_Msk (0x1UL << GOTGCTL_OTGVER_Pos) // 0x00100000
743#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk // OTG version
744
745/******************** Bit definition for HCFG register ********************/
746#define HCFG_FSLS_PHYCLK_SEL_Pos (0U)
747#define HCFG_FSLS_PHYCLK_SEL_Msk (0x3UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000003
748#define HCFG_FSLS_PHYCLK_SEL HCFG_FSLS_PHYCLK_SEL_Msk // FS/LS PHY clock select
749#define HCFG_FSLS_PHYCLK_SEL_30_60MHZ (0x0UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000000
750#define HCFG_FSLS_PHYCLK_SEL_48MHZ (0x1UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000001
751#define HCFG_FSLS_PHYCLK_SEL_6MHZ (0x2UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000002
752
753#define HCFG_FSLS_ONLY_Pos (2U)
754#define HCFG_FSLS_ONLY_Msk (0x1UL << HCFG_FSLS_ONLY_Pos) // 0x00000004
755#define HCFG_FSLS_ONLY HCFG_FSLS_ONLY_Msk // FS- and LS-only support
756
757/******************** Bit definition for PCGCR register ********************/
758#define PCGCR_STPPCLK_Pos (0U)
759#define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) // 0x00000001
760#define PCGCR_STPPCLK PCGCR_STPPCLK_Msk // Stop PHY clock
761#define PCGCR_GATEHCLK_Pos (1U)
762#define PCGCR_GATEHCLK_Msk (0x1UL << PCGCR_GATEHCLK_Pos) // 0x00000002
763#define PCGCR_GATEHCLK PCGCR_GATEHCLK_Msk // Gate HCLK
764#define PCGCR_PHYSUSP_Pos (4U)
765#define PCGCR_PHYSUSP_Msk (0x1UL << PCGCR_PHYSUSP_Pos) // 0x00000010
766#define PCGCR_PHYSUSP PCGCR_PHYSUSP_Msk // PHY suspended
767
768/******************** Bit definition for GOTGINT register ********************/
769#define GOTGINT_SEDET_Pos (2U)
770#define GOTGINT_SEDET_Msk (0x1UL << GOTGINT_SEDET_Pos) // 0x00000004
771#define GOTGINT_SEDET GOTGINT_SEDET_Msk // Session end detected
772#define GOTGINT_SRSSCHG_Pos (8U)
773#define GOTGINT_SRSSCHG_Msk (0x1UL << GOTGINT_SRSSCHG_Pos) // 0x00000100
774#define GOTGINT_SRSSCHG GOTGINT_SRSSCHG_Msk // Session request success status change
775#define GOTGINT_HNSSCHG_Pos (9U)
776#define GOTGINT_HNSSCHG_Msk (0x1UL << GOTGINT_HNSSCHG_Pos) // 0x00000200
777#define GOTGINT_HNSSCHG GOTGINT_HNSSCHG_Msk // Host negotiation success status change
778#define GOTGINT_HNGDET_Pos (17U)
779#define GOTGINT_HNGDET_Msk (0x1UL << GOTGINT_HNGDET_Pos) // 0x00020000
780#define GOTGINT_HNGDET GOTGINT_HNGDET_Msk // Host negotiation detected
781#define GOTGINT_ADTOCHG_Pos (18U)
782#define GOTGINT_ADTOCHG_Msk (0x1UL << GOTGINT_ADTOCHG_Pos) // 0x00040000
783#define GOTGINT_ADTOCHG GOTGINT_ADTOCHG_Msk // A-device timeout change
784#define GOTGINT_DBCDNE_Pos (19U)
785#define GOTGINT_DBCDNE_Msk (0x1UL << GOTGINT_DBCDNE_Pos) // 0x00080000
786#define GOTGINT_DBCDNE GOTGINT_DBCDNE_Msk // Debounce done
787#define GOTGINT_IDCHNG_Pos (20U)
788#define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) // 0x00100000
789#define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk // Change in ID pin input value
790
791/******************** Bit definition for DCFG register ********************/
792#define DCFG_DSPD_Pos (0U)
793#define DCFG_DSPD_Msk (0x3UL << DCFG_DSPD_Pos) // 0x00000003
794#define DCFG_DSPD_HS 0 // Highspeed
795#define DCFG_DSPD_FS_HSPHY 1 // Fullspeed on HS PHY
796#define DCFG_DSPD_LS 2 // Lowspeed
797#define DCFG_DSPD_FS 3 // Fullspeed on FS PHY
798
799#define DCFG_NZLSOHSK_Pos (2U)
800#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) // 0x00000004
801#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk // Nonzero-length status OUT handshake
802
803#define DCFG_DAD_Pos (4U)
804#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) // 0x000007F0
805#define DCFG_DAD DCFG_DAD_Msk // Device address
806#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) // 0x00000010
807#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) // 0x00000020
808#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) // 0x00000040
809#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) // 0x00000080
810#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) // 0x00000100
811#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) // 0x00000200
812#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) // 0x00000400
813
814#define DCFG_PFIVL_Pos (11U)
815#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) // 0x00001800
816#define DCFG_PFIVL DCFG_PFIVL_Msk // Periodic (micro)frame interval
817#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800
818#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000
819
820#define DCFG_XCVRDLY_Pos (14U)
821#define DCFG_XCVRDLY_Msk (0x1UL << DCFG_XCVRDLY_Pos) // 0x00004000
822#define DCFG_XCVRDLY DCFG_XCVRDLY_Msk // Enables delay between xcvr_sel and txvalid during device chirp
823
824#define DCFG_PERSCHIVL_Pos (24U)
825#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000
826#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval
827#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) // 0x01000000
828#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) // 0x02000000
829
830/******************** Bit definition for DCTL register ********************/
831#define DCTL_RWUSIG_Pos (0U)
832#define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) // 0x00000001
833#define DCTL_RWUSIG DCTL_RWUSIG_Msk // Remote wakeup signaling
834#define DCTL_SDIS_Pos (1U)
835#define DCTL_SDIS_Msk (0x1UL << DCTL_SDIS_Pos) // 0x00000002
836#define DCTL_SDIS DCTL_SDIS_Msk // Soft disconnect
837#define DCTL_GINSTS_Pos (2U)
838#define DCTL_GINSTS_Msk (0x1UL << DCTL_GINSTS_Pos) // 0x00000004
839#define DCTL_GINSTS DCTL_GINSTS_Msk // Global IN NAK status
840#define DCTL_GONSTS_Pos (3U)
841#define DCTL_GONSTS_Msk (0x1UL << DCTL_GONSTS_Pos) // 0x00000008
842#define DCTL_GONSTS DCTL_GONSTS_Msk // Global OUT NAK status
843
844#define DCTL_TCTL_Pos (4U)
845#define DCTL_TCTL_Msk (0x7UL << DCTL_TCTL_Pos) // 0x00000070
846#define DCTL_TCTL DCTL_TCTL_Msk // Test control
847#define DCTL_TCTL_0 (0x1UL << DCTL_TCTL_Pos) // 0x00000010
848#define DCTL_TCTL_1 (0x2UL << DCTL_TCTL_Pos) // 0x00000020
849#define DCTL_TCTL_2 (0x4UL << DCTL_TCTL_Pos) // 0x00000040
850#define DCTL_SGINAK_Pos (7U)
851#define DCTL_SGINAK_Msk (0x1UL << DCTL_SGINAK_Pos) // 0x00000080
852#define DCTL_SGINAK DCTL_SGINAK_Msk // Set global IN NAK
853#define DCTL_CGINAK_Pos (8U)
854#define DCTL_CGINAK_Msk (0x1UL << DCTL_CGINAK_Pos) // 0x00000100
855#define DCTL_CGINAK DCTL_CGINAK_Msk // Clear global IN NAK
856#define DCTL_SGONAK_Pos (9U)
857#define DCTL_SGONAK_Msk (0x1UL << DCTL_SGONAK_Pos) // 0x00000200
858#define DCTL_SGONAK DCTL_SGONAK_Msk // Set global OUT NAK
859#define DCTL_CGONAK_Pos (10U)
860#define DCTL_CGONAK_Msk (0x1UL << DCTL_CGONAK_Pos) // 0x00000400
861#define DCTL_CGONAK DCTL_CGONAK_Msk // Clear global OUT NAK
862#define DCTL_POPRGDNE_Pos (11U)
863#define DCTL_POPRGDNE_Msk (0x1UL << DCTL_POPRGDNE_Pos) // 0x00000800
864#define DCTL_POPRGDNE DCTL_POPRGDNE_Msk // Power-on programming done
865
866/******************** Bit definition for HFIR register ********************/
867#define HFIR_FRIVL_Pos (0U)
868#define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) // 0x0000FFFF
869#define HFIR_FRIVL HFIR_FRIVL_Msk // Frame interval
870#define HFIR_RELOAD_CTRL_Pos (16U) // available since v2.92a
871#define HFIR_RELOAD_CTRL_Msk (0x1UL << HFIR_RELOAD_CTRL_Pos)
872#define HFIR_RELOAD_CTRL HFIR_RELOAD_CTRL_Msk
873
874/******************** Bit definition for HFNUM register ********************/
875#define HFNUM_FRNUM_Pos (0U)
876#define HFNUM_FRNUM_Msk (0xFFFFUL << HFNUM_FRNUM_Pos) // 0x0000FFFF
877#define HFNUM_FRNUM HFNUM_FRNUM_Msk // Frame number
878#define HFNUM_FTREM_Pos (16U)
879#define HFNUM_FTREM_Msk (0xFFFFUL << HFNUM_FTREM_Pos) // 0xFFFF0000
880#define HFNUM_FTREM HFNUM_FTREM_Msk // Frame time remaining
881
882/******************** Bit definition for DSTS register ********************/
883#define DSTS_SUSPSTS_Pos (0U)
884#define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) // 0x00000001
885#define DSTS_SUSPSTS DSTS_SUSPSTS_Msk // Suspend status
886#define DSTS_ENUMSPD_Pos (1U)
887#define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) // 0x00000006
888#define DSTS_ENUMSPD DSTS_ENUMSPD_Msk // Enumerated speed
889#define DSTS_ENUMSPD_HS 0 // Highspeed
890#define DSTS_ENUMSPD_FS_HSPHY 1 // Fullspeed on HS PHY
891#define DSTS_ENUMSPD_LS 2 // Lowspeed
892#define DSTS_ENUMSPD_FS 3 // Fullspeed on FS PHY
893
894
895#define DSTS_EERR_Pos (3U)
896#define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) // 0x00000008
897#define DSTS_EERR DSTS_EERR_Msk // Erratic error
898#define DSTS_FNSOF_Pos (8U)
899#define DSTS_FNSOF_Msk (0x3FFFUL << DSTS_FNSOF_Pos) // 0x003FFF00
900#define DSTS_FNSOF DSTS_FNSOF_Msk // Frame number of the received SOF
901
902/******************** Bit definition for GAHBCFG register ********************/
903#define GAHBCFG_GINT_Pos (0U)
904#define GAHBCFG_GINT_Msk (0x1UL << GAHBCFG_GINT_Pos) // 0x00000001
905#define GAHBCFG_GINT GAHBCFG_GINT_Msk // Global interrupt mask
906#define GAHBCFG_HBSTLEN_Pos (1U)
907#define GAHBCFG_HBSTLEN_Msk (0xFUL << GAHBCFG_HBSTLEN_Pos) // 0x0000001E
908#define GAHBCFG_HBSTLEN GAHBCFG_HBSTLEN_Msk // Burst length/type
909#define GAHBCFG_HBSTLEN_0 (0x0UL << GAHBCFG_HBSTLEN_Pos) // Single
910#define GAHBCFG_HBSTLEN_1 (0x1UL << GAHBCFG_HBSTLEN_Pos) // INCR
911#define GAHBCFG_HBSTLEN_2 (0x3UL << GAHBCFG_HBSTLEN_Pos) // INCR4
912#define GAHBCFG_HBSTLEN_3 (0x5UL << GAHBCFG_HBSTLEN_Pos) // INCR8
913#define GAHBCFG_HBSTLEN_4 (0x7UL << GAHBCFG_HBSTLEN_Pos) // INCR16
914#define GAHBCFG_DMAEN_Pos (5U)
915#define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) // 0x00000020
916#define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk // DMA enable
917#define GAHBCFG_TX_FIFO_EPMTY_LVL_Pos (7U)
918#define GAHBCFG_TX_FIFO_EPMTY_LVL_Msk (0x1UL << GAHBCFG_TX_FIFO_EPMTY_LVL_Pos) // 0x00000080
919#define GAHBCFG_TX_FIFO_EPMTY_LVL GAHBCFG_TX_FIFO_EPMTY_LVL_Msk // TxFIFO empty level
920#define GAHBCFG_PTX_FIFO_EPMTY_LVL_Pos (8U)
921#define GAHBCFG_PTX_FIFO_EPMTY_LVL_Msk (0x1UL << GAHBCFG_PTX_FIFO_EPMTY_LVL_Pos) // 0x00000100
922#define GAHBCFG_PTX_FIFO_EPMTY_LVL GAHBCFG_PTX_FIFO_EPMTY_LVL_Msk // Periodic TxFIFO empty level
923
924/******************** Bit definition for GUSBCFG register ********************/
925#define GUSBCFG_TOCAL_Pos (0U)
926#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007
927#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // HS/FS timeout calibration
928#define GUSBCFG_PHYIF16_Pos (3U)
929#define GUSBCFG_PHYIF16_Msk (0x1UL << GUSBCFG_PHYIF16_Pos) // 0x00000008
930#define GUSBCFG_PHYIF16 GUSBCFG_PHYIF16_Msk // PHY Interface (PHYIf)
931#define GUSBCFG_ULPI_UTMI_SEL_Pos (4U)
932#define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) // 0x00000010
933#define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk // ULPI or UTMI+ Select (ULPI_UTMI_Sel)
934#define GUSBCFG_PHYSEL_Pos (6U)
935#define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) // 0x00000040
936#define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
937#define GUSBCFG_DDRSEL TU_BIT(7) // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
938#define GUSBCFG_SRPCAP_Pos (8U)
939#define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) // 0x00000100
940#define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk // SRP-capable
941#define GUSBCFG_HNPCAP_Pos (9U)
942#define GUSBCFG_HNPCAP_Msk (0x1UL << GUSBCFG_HNPCAP_Pos) // 0x00000200
943#define GUSBCFG_HNPCAP GUSBCFG_HNPCAP_Msk // HNP-capable
944#define GUSBCFG_TRDT_Pos (10U)
945#define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) // 0x00003C00
946#define GUSBCFG_TRDT GUSBCFG_TRDT_Msk // USB turnaround time
947#define GUSBCFG_PHYLPCS_Pos (15U)
948#define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) // 0x00008000
949#define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk // PHY Low-power clock select
950#define GUSBCFG_ULPIFSLS_Pos (17U)
951#define GUSBCFG_ULPIFSLS_Msk (0x1UL << GUSBCFG_ULPIFSLS_Pos) // 0x00020000
952#define GUSBCFG_ULPIFSLS GUSBCFG_ULPIFSLS_Msk // ULPI FS/LS select
953#define GUSBCFG_ULPIAR_Pos (18U)
954#define GUSBCFG_ULPIAR_Msk (0x1UL << GUSBCFG_ULPIAR_Pos) // 0x00040000
955#define GUSBCFG_ULPIAR GUSBCFG_ULPIAR_Msk // ULPI Auto-resume
956#define GUSBCFG_ULPICSM_Pos (19U)
957#define GUSBCFG_ULPICSM_Msk (0x1UL << GUSBCFG_ULPICSM_Pos) // 0x00080000
958#define GUSBCFG_ULPICSM GUSBCFG_ULPICSM_Msk // ULPI Clock SuspendM
959#define GUSBCFG_ULPIEVBUSD_Pos (20U)
960#define GUSBCFG_ULPIEVBUSD_Msk (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) // 0x00100000
961#define GUSBCFG_ULPIEVBUSD GUSBCFG_ULPIEVBUSD_Msk // ULPI External VBUS Drive
962#define GUSBCFG_ULPIEVBUSI_Pos (21U)
963#define GUSBCFG_ULPIEVBUSI_Msk (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) // 0x00200000
964#define GUSBCFG_ULPIEVBUSI GUSBCFG_ULPIEVBUSI_Msk // ULPI external VBUS indicator
965#define GUSBCFG_TSDPS_Pos (22U)
966#define GUSBCFG_TSDPS_Msk (0x1UL << GUSBCFG_TSDPS_Pos) // 0x00400000
967#define GUSBCFG_TSDPS GUSBCFG_TSDPS_Msk // TermSel DLine pulsing selection
968#define GUSBCFG_PCCI_Pos (23U)
969#define GUSBCFG_PCCI_Msk (0x1UL << GUSBCFG_PCCI_Pos) // 0x00800000
970#define GUSBCFG_PCCI GUSBCFG_PCCI_Msk // Indicator complement
971#define GUSBCFG_PTCI_Pos (24U)
972#define GUSBCFG_PTCI_Msk (0x1UL << GUSBCFG_PTCI_Pos) // 0x01000000
973#define GUSBCFG_PTCI GUSBCFG_PTCI_Msk // Indicator pass through
974#define GUSBCFG_ULPIIPD_Pos (25U)
975#define GUSBCFG_ULPIIPD_Msk (0x1UL << GUSBCFG_ULPIIPD_Pos) // 0x02000000
976#define GUSBCFG_ULPIIPD GUSBCFG_ULPIIPD_Msk // ULPI interface protect disable
977#define GUSBCFG_FHMOD_Pos (29U)
978#define GUSBCFG_FHMOD_Msk (0x1UL << GUSBCFG_FHMOD_Pos) // 0x20000000
979#define GUSBCFG_FHMOD GUSBCFG_FHMOD_Msk // Forced host mode
980#define GUSBCFG_FDMOD_Pos (30U)
981#define GUSBCFG_FDMOD_Msk (0x1UL << GUSBCFG_FDMOD_Pos) // 0x40000000
982#define GUSBCFG_FDMOD GUSBCFG_FDMOD_Msk // Forced peripheral mode
983#define GUSBCFG_CTXPKT_Pos (31U)
984#define GUSBCFG_CTXPKT_Msk (0x1UL << GUSBCFG_CTXPKT_Pos) // 0x80000000
985#define GUSBCFG_CTXPKT GUSBCFG_CTXPKT_Msk // Corrupt Tx packet
986
987/******************** Bit definition for GRSTCTL register ********************/
988#define GRSTCTL_CSRST_Pos (0U)
989#define GRSTCTL_CSRST_Msk (0x1UL << GRSTCTL_CSRST_Pos) // 0x00000001
990#define GRSTCTL_CSRST GRSTCTL_CSRST_Msk // Core soft reset
991#define GRSTCTL_HSRST_Pos (1U)
992#define GRSTCTL_HSRST_Msk (0x1UL << GRSTCTL_HSRST_Pos) // 0x00000002
993#define GRSTCTL_HSRST GRSTCTL_HSRST_Msk // HCLK soft reset
994#define GRSTCTL_FCRST_Pos (2U)
995#define GRSTCTL_FCRST_Msk (0x1UL << GRSTCTL_FCRST_Pos) // 0x00000004
996#define GRSTCTL_FCRST GRSTCTL_FCRST_Msk // Host frame counter reset
997#define GRSTCTL_RXFFLSH_Pos (4U)
998#define GRSTCTL_RXFFLSH_Msk (0x1UL << GRSTCTL_RXFFLSH_Pos) // 0x00000010
999#define GRSTCTL_RXFFLSH GRSTCTL_RXFFLSH_Msk // RxFIFO flush
1000#define GRSTCTL_TXFFLSH_Pos (5U)
1001#define GRSTCTL_TXFFLSH_Msk (0x1UL << GRSTCTL_TXFFLSH_Pos) // 0x00000020
1002#define GRSTCTL_TXFFLSH GRSTCTL_TXFFLSH_Msk // TxFIFO flush
1003#define GRSTCTL_TXFNUM_Pos (6U)
1004#define GRSTCTL_TXFNUM_Msk (0x1FUL << GRSTCTL_TXFNUM_Pos) // 0x000007C0
1005#define GRSTCTL_TXFNUM GRSTCTL_TXFNUM_Msk // TxFIFO number
1006#define GRSTCTL_TXFNUM_0 (0x01UL << GRSTCTL_TXFNUM_Pos) // 0x00000040
1007#define GRSTCTL_TXFNUM_1 (0x02UL << GRSTCTL_TXFNUM_Pos) // 0x00000080
1008#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100
1009#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200
1010#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400
1011#define GRSTCTL_CSRST_DONE_Pos (29)
1012#define GRSTCTL_CSRST_DONE (1u << GRSTCTL_CSRST_DONE_Pos) // Reset Done, only available from v4.20a
1013#define GRSTCTL_DMAREQ_Pos (30U)
1014#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000
1015#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal
1016#define GRSTCTL_AHBIDL_Pos (31U)
1017#define GRSTCTL_AHBIDL_Msk (0x1UL << GRSTCTL_AHBIDL_Pos) // 0x80000000
1018#define GRSTCTL_AHBIDL GRSTCTL_AHBIDL_Msk // AHB master idle
1019
1020/******************** Bit definition for DIEPMSK register ********************/
1021#define DIEPMSK_XFRCM_Pos (0U)
1022#define DIEPMSK_XFRCM_Msk (0x1UL << DIEPMSK_XFRCM_Pos) // 0x00000001
1023#define DIEPMSK_XFRCM DIEPMSK_XFRCM_Msk // Transfer completed interrupt mask
1024#define DIEPMSK_EPDM_Pos (1U)
1025#define DIEPMSK_EPDM_Msk (0x1UL << DIEPMSK_EPDM_Pos) // 0x00000002
1026#define DIEPMSK_EPDM DIEPMSK_EPDM_Msk // Endpoint disabled interrupt mask
1027#define DIEPMSK_TOM_Pos (3U)
1028#define DIEPMSK_TOM_Msk (0x1UL << DIEPMSK_TOM_Pos) // 0x00000008
1029#define DIEPMSK_TOM DIEPMSK_TOM_Msk // Timeout condition mask (nonisochronous endpoints)
1030#define DIEPMSK_ITTXFEMSK_Pos (4U)
1031#define DIEPMSK_ITTXFEMSK_Msk (0x1UL << DIEPMSK_ITTXFEMSK_Pos) // 0x00000010
1032#define DIEPMSK_ITTXFEMSK DIEPMSK_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask
1033#define DIEPMSK_INEPNMM_Pos (5U)
1034#define DIEPMSK_INEPNMM_Msk (0x1UL << DIEPMSK_INEPNMM_Pos) // 0x00000020
1035#define DIEPMSK_INEPNMM DIEPMSK_INEPNMM_Msk // IN token received with EP mismatch mask
1036#define DIEPMSK_INEPNEM_Pos (6U)
1037#define DIEPMSK_INEPNEM_Msk (0x1UL << DIEPMSK_INEPNEM_Pos) // 0x00000040
1038#define DIEPMSK_INEPNEM DIEPMSK_INEPNEM_Msk // IN endpoint NAK effective mask
1039#define DIEPMSK_TXFURM_Pos (8U)
1040#define DIEPMSK_TXFURM_Msk (0x1UL << DIEPMSK_TXFURM_Pos) // 0x00000100
1041#define DIEPMSK_TXFURM DIEPMSK_TXFURM_Msk // FIFO underrun mask
1042#define DIEPMSK_BIM_Pos (9U)
1043#define DIEPMSK_BIM_Msk (0x1UL << DIEPMSK_BIM_Pos) // 0x00000200
1044#define DIEPMSK_BIM DIEPMSK_BIM_Msk // BNA interrupt mask
1045
1046/******************** Bit definition for HPTXSTS register ********************/
1047#define HPTXSTS_PTXFSAVL_Pos (0U)
1048#define HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) // 0x0000FFFF
1049#define HPTXSTS_PTXFSAVL HPTXSTS_PTXFSAVL_Msk // Periodic transmit data FIFO space available
1050#define HPTXSTS_PTXQSAV_Pos (16U)
1051#define HPTXSTS_PTXQSAV_Msk (0xFFUL << HPTXSTS_PTXQSAV_Pos) // 0x00FF0000
1052#define HPTXSTS_PTXQSAV HPTXSTS_PTXQSAV_Msk // Periodic transmit request queue space available
1053#define HPTXSTS_PTXQSAV_0 (0x01UL << HPTXSTS_PTXQSAV_Pos) // 0x00010000
1054#define HPTXSTS_PTXQSAV_1 (0x02UL << HPTXSTS_PTXQSAV_Pos) // 0x00020000
1055#define HPTXSTS_PTXQSAV_2 (0x04UL << HPTXSTS_PTXQSAV_Pos) // 0x00040000
1056#define HPTXSTS_PTXQSAV_3 (0x08UL << HPTXSTS_PTXQSAV_Pos) // 0x00080000
1057#define HPTXSTS_PTXQSAV_4 (0x10UL << HPTXSTS_PTXQSAV_Pos) // 0x00100000
1058#define HPTXSTS_PTXQSAV_5 (0x20UL << HPTXSTS_PTXQSAV_Pos) // 0x00200000
1059#define HPTXSTS_PTXQSAV_6 (0x40UL << HPTXSTS_PTXQSAV_Pos) // 0x00400000
1060#define HPTXSTS_PTXQSAV_7 (0x80UL << HPTXSTS_PTXQSAV_Pos) // 0x00800000
1061
1062#define HPTXSTS_PTXQTOP_Pos (24U)
1063#define HPTXSTS_PTXQTOP_Msk (0xFFUL << HPTXSTS_PTXQTOP_Pos) // 0xFF000000
1064#define HPTXSTS_PTXQTOP HPTXSTS_PTXQTOP_Msk // Top of the periodic transmit request queue
1065#define HPTXSTS_PTXQTOP_0 (0x01UL << HPTXSTS_PTXQTOP_Pos) // 0x01000000
1066#define HPTXSTS_PTXQTOP_1 (0x02UL << HPTXSTS_PTXQTOP_Pos) // 0x02000000
1067#define HPTXSTS_PTXQTOP_2 (0x04UL << HPTXSTS_PTXQTOP_Pos) // 0x04000000
1068#define HPTXSTS_PTXQTOP_3 (0x08UL << HPTXSTS_PTXQTOP_Pos) // 0x08000000
1069#define HPTXSTS_PTXQTOP_4 (0x10UL << HPTXSTS_PTXQTOP_Pos) // 0x10000000
1070#define HPTXSTS_PTXQTOP_5 (0x20UL << HPTXSTS_PTXQTOP_Pos) // 0x20000000
1071#define HPTXSTS_PTXQTOP_6 (0x40UL << HPTXSTS_PTXQTOP_Pos) // 0x40000000
1072#define HPTXSTS_PTXQTOP_7 (0x80UL << HPTXSTS_PTXQTOP_Pos) // 0x80000000
1073
1074/******************** Bit definition for HAINT register ********************/
1075#define HAINT_HAINT_Pos (0U)
1076#define HAINT_HAINT_Msk (0xFFFFUL << HAINT_HAINT_Pos) // 0x0000FFFF
1077#define HAINT_HAINT HAINT_HAINT_Msk // Channel interrupts
1078
1079/******************** Bit definition for DOEPMSK register ********************/
1080#define DOEPMSK_XFRCM_Pos (0U)
1081#define DOEPMSK_XFRCM_Msk (0x1UL << DOEPMSK_XFRCM_Pos) // 0x00000001
1082#define DOEPMSK_XFRCM DOEPMSK_XFRCM_Msk // Transfer completed interrupt mask
1083#define DOEPMSK_EPDM_Pos (1U)
1084#define DOEPMSK_EPDM_Msk (0x1UL << DOEPMSK_EPDM_Pos) // 0x00000002
1085#define DOEPMSK_EPDM DOEPMSK_EPDM_Msk // Endpoint disabled interrupt mask
1086#define DOEPMSK_AHBERRM_Pos (2U)
1087#define DOEPMSK_AHBERRM_Msk (0x1UL << DOEPMSK_AHBERRM_Pos) // 0x00000004
1088#define DOEPMSK_AHBERRM DOEPMSK_AHBERRM_Msk // OUT transaction AHB Error interrupt mask
1089#define DOEPMSK_STUPM_Pos (3U)
1090#define DOEPMSK_STUPM_Msk (0x1UL << DOEPMSK_STUPM_Pos) // 0x00000008
1091#define DOEPMSK_STUPM DOEPMSK_STUPM_Msk // SETUP phase done mask
1092#define DOEPMSK_OTEPDM_Pos (4U)
1093#define DOEPMSK_OTEPDM_Msk (0x1UL << DOEPMSK_OTEPDM_Pos) // 0x00000010
1094#define DOEPMSK_OTEPDM DOEPMSK_OTEPDM_Msk // OUT token received when endpoint disabled mask
1095#define DOEPMSK_OTEPSPRM_Pos (5U)
1096#define DOEPMSK_OTEPSPRM_Msk (0x1UL << DOEPMSK_OTEPSPRM_Pos) // 0x00000020
1097#define DOEPMSK_OTEPSPRM DOEPMSK_OTEPSPRM_Msk // Status Phase Received mask
1098#define DOEPMSK_B2BSTUP_Pos (6U)
1099#define DOEPMSK_B2BSTUP_Msk (0x1UL << DOEPMSK_B2BSTUP_Pos) // 0x00000040
1100#define DOEPMSK_B2BSTUP DOEPMSK_B2BSTUP_Msk // Back-to-back SETUP packets received mask
1101#define DOEPMSK_OPEM_Pos (8U)
1102#define DOEPMSK_OPEM_Msk (0x1UL << DOEPMSK_OPEM_Pos) // 0x00000100
1103#define DOEPMSK_OPEM DOEPMSK_OPEM_Msk // OUT packet error mask
1104#define DOEPMSK_BOIM_Pos (9U)
1105#define DOEPMSK_BOIM_Msk (0x1UL << DOEPMSK_BOIM_Pos) // 0x00000200
1106#define DOEPMSK_BOIM DOEPMSK_BOIM_Msk // BNA interrupt mask
1107#define DOEPMSK_BERRM_Pos (12U)
1108#define DOEPMSK_BERRM_Msk (0x1UL << DOEPMSK_BERRM_Pos) // 0x00001000
1109#define DOEPMSK_BERRM DOEPMSK_BERRM_Msk // Babble error interrupt mask
1110#define DOEPMSK_NAKM_Pos (13U)
1111#define DOEPMSK_NAKM_Msk (0x1UL << DOEPMSK_NAKM_Pos) // 0x00002000
1112#define DOEPMSK_NAKM DOEPMSK_NAKM_Msk // OUT Packet NAK interrupt mask
1113#define DOEPMSK_NYETM_Pos (14U)
1114#define DOEPMSK_NYETM_Msk (0x1UL << DOEPMSK_NYETM_Pos) // 0x00004000
1115#define DOEPMSK_NYETM DOEPMSK_NYETM_Msk // NYET interrupt mask
1116
1117/******************** Bit definition for GINTSTS register ********************/
1118#define GINTSTS_CMOD_Pos (0U)
1119#define GINTSTS_CMOD_Msk (0x1UL << GINTSTS_CMOD_Pos) // 0x00000001
1120#define GINTSTS_CMOD GINTSTS_CMOD_Msk // Current mode of operation
1121#define GINTSTS_MMIS_Pos (1U)
1122#define GINTSTS_MMIS_Msk (0x1UL << GINTSTS_MMIS_Pos) // 0x00000002
1123#define GINTSTS_MMIS GINTSTS_MMIS_Msk // Mode mismatch interrupt
1124#define GINTSTS_OTGINT_Pos (2U)
1125#define GINTSTS_OTGINT_Msk (0x1UL << GINTSTS_OTGINT_Pos) // 0x00000004
1126#define GINTSTS_OTGINT GINTSTS_OTGINT_Msk // OTG interrupt
1127#define GINTSTS_SOF_Pos (3U)
1128#define GINTSTS_SOF_Msk (0x1UL << GINTSTS_SOF_Pos) // 0x00000008
1129#define GINTSTS_SOF GINTSTS_SOF_Msk // Start of frame
1130#define GINTSTS_RXFLVL_Pos (4U)
1131#define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) // 0x00000010
1132#define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk // RxFIFO nonempty
1133#define GINTSTS_NPTX_FIFO_EMPTY_Pos (5U)
1134#define GINTSTS_NPTX_FIFO_EMPTY_Msk (0x1UL << GINTSTS_NPTX_FIFO_EMPTY_Pos) // 0x00000020
1135#define GINTSTS_NPTX_FIFO_EMPTY GINTSTS_NPTX_FIFO_EMPTY_Msk // Nonperiodic TxFIFO empty
1136#define GINTSTS_GINAKEFF_Pos (6U)
1137#define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) // 0x00000040
1138#define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk // Global IN nonperiodic NAK effective
1139#define GINTSTS_BOUTNAKEFF_Pos (7U)
1140#define GINTSTS_BOUTNAKEFF_Msk (0x1UL << GINTSTS_BOUTNAKEFF_Pos) // 0x00000080
1141#define GINTSTS_BOUTNAKEFF GINTSTS_BOUTNAKEFF_Msk // Global OUT NAK effective
1142#define GINTSTS_ESUSP_Pos (10U)
1143#define GINTSTS_ESUSP_Msk (0x1UL << GINTSTS_ESUSP_Pos) // 0x00000400
1144#define GINTSTS_ESUSP GINTSTS_ESUSP_Msk // Early suspend
1145#define GINTSTS_USBSUSP_Pos (11U)
1146#define GINTSTS_USBSUSP_Msk (0x1UL << GINTSTS_USBSUSP_Pos) // 0x00000800
1147#define GINTSTS_USBSUSP GINTSTS_USBSUSP_Msk // USB suspend
1148#define GINTSTS_USBRST_Pos (12U)
1149#define GINTSTS_USBRST_Msk (0x1UL << GINTSTS_USBRST_Pos) // 0x00001000
1150#define GINTSTS_USBRST GINTSTS_USBRST_Msk // USB reset
1151#define GINTSTS_ENUMDNE_Pos (13U)
1152#define GINTSTS_ENUMDNE_Msk (0x1UL << GINTSTS_ENUMDNE_Pos) // 0x00002000
1153#define GINTSTS_ENUMDNE GINTSTS_ENUMDNE_Msk // Enumeration done
1154#define GINTSTS_ISOODRP_Pos (14U)
1155#define GINTSTS_ISOODRP_Msk (0x1UL << GINTSTS_ISOODRP_Pos) // 0x00004000
1156#define GINTSTS_ISOODRP GINTSTS_ISOODRP_Msk // Isochronous OUT packet dropped interrupt
1157#define GINTSTS_EOPF_Pos (15U)
1158#define GINTSTS_EOPF_Msk (0x1UL << GINTSTS_EOPF_Pos) // 0x00008000
1159#define GINTSTS_EOPF GINTSTS_EOPF_Msk // End of periodic frame interrupt
1160#define GINTSTS_IEPINT_Pos (18U)
1161#define GINTSTS_IEPINT_Msk (0x1UL << GINTSTS_IEPINT_Pos) // 0x00040000
1162#define GINTSTS_IEPINT GINTSTS_IEPINT_Msk // IN endpoint interrupt
1163#define GINTSTS_OEPINT_Pos (19U)
1164#define GINTSTS_OEPINT_Msk (0x1UL << GINTSTS_OEPINT_Pos) // 0x00080000
1165#define GINTSTS_OEPINT GINTSTS_OEPINT_Msk // OUT endpoint interrupt
1166#define GINTSTS_IISOIXFR_Pos (20U)
1167#define GINTSTS_IISOIXFR_Msk (0x1UL << GINTSTS_IISOIXFR_Pos) // 0x00100000
1168#define GINTSTS_IISOIXFR GINTSTS_IISOIXFR_Msk // Incomplete isochronous IN transfer
1169#define GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
1170#define GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000
1171#define GINTSTS_PXFR_INCOMPISOOUT GINTSTS_PXFR_INCOMPISOOUT_Msk // Incomplete periodic transfer
1172#define GINTSTS_DATAFSUSP_Pos (22U)
1173#define GINTSTS_DATAFSUSP_Msk (0x1UL << GINTSTS_DATAFSUSP_Pos) // 0x00400000
1174#define GINTSTS_DATAFSUSP GINTSTS_DATAFSUSP_Msk // Data fetch suspended
1175#define GINTSTS_RSTDET_Pos (23U)
1176#define GINTSTS_RSTDET_Msk (0x1UL << GINTSTS_RSTDET_Pos) // 0x00800000
1177#define GINTSTS_RSTDET GINTSTS_RSTDET_Msk // Reset detected interrupt
1178#define GINTSTS_HPRTINT_Pos (24U)
1179#define GINTSTS_HPRTINT_Msk (0x1UL << GINTSTS_HPRTINT_Pos) // 0x01000000
1180#define GINTSTS_HPRTINT GINTSTS_HPRTINT_Msk // Host port interrupt
1181#define GINTSTS_HCINT_Pos (25U)
1182#define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) // 0x02000000
1183#define GINTSTS_HCINT GINTSTS_HCINT_Msk // Host channels interrupt
1184#define GINTSTS_PTX_FIFO_EMPTY_Pos (26U)
1185#define GINTSTS_PTX_FIFO_EMPTY_Msk (0x1UL << GINTSTS_PTX_FIFO_EMPTY_Pos) // 0x04000000
1186#define GINTSTS_PTX_FIFO_EMPTY GINTSTS_PTX_FIFO_EMPTY_Msk // Periodic TxFIFO empty
1187#define GINTSTS_LPMINT_Pos (27U)
1188#define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) // 0x08000000
1189#define GINTSTS_LPMINT GINTSTS_LPMINT_Msk // LPM interrupt
1190#define GINTSTS_CONIDSTSCHNG_Pos (28U)
1191#define GINTSTS_CONIDSTSCHNG_Msk (0x1UL << GINTSTS_CONIDSTSCHNG_Pos) // 0x10000000
1192#define GINTSTS_CONIDSTSCHNG GINTSTS_CONIDSTSCHNG_Msk // Connector ID status change
1193#define GINTSTS_DISCINT_Pos (29U)
1194#define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) // 0x20000000
1195#define GINTSTS_DISCINT GINTSTS_DISCINT_Msk // Disconnect detected interrupt
1196#define GINTSTS_SRQINT_Pos (30U)
1197#define GINTSTS_SRQINT_Msk (0x1UL << GINTSTS_SRQINT_Pos) // 0x40000000
1198#define GINTSTS_SRQINT GINTSTS_SRQINT_Msk // Session request/new session detected interrupt
1199#define GINTSTS_WKUINT_Pos (31U)
1200#define GINTSTS_WKUINT_Msk (0x1UL << GINTSTS_WKUINT_Pos) // 0x80000000
1201#define GINTSTS_WKUINT GINTSTS_WKUINT_Msk // Resume/remote wakeup detected interrupt
1202
1203/******************** Bit definition for GINTMSK register ********************/
1204#define GINTMSK_MMISM_Pos (1U)
1205#define GINTMSK_MMISM_Msk (0x1UL << GINTMSK_MMISM_Pos) // 0x00000002
1206#define GINTMSK_MMISM GINTMSK_MMISM_Msk // Mode mismatch interrupt mask
1207#define GINTMSK_OTGINT_Pos (2U)
1208#define GINTMSK_OTGINT_Msk (0x1UL << GINTMSK_OTGINT_Pos) // 0x00000004
1209#define GINTMSK_OTGINT GINTMSK_OTGINT_Msk // OTG interrupt mask
1210#define GINTMSK_SOFM_Pos (3U)
1211#define GINTMSK_SOFM_Msk (0x1UL << GINTMSK_SOFM_Pos) // 0x00000008
1212#define GINTMSK_SOFM GINTMSK_SOFM_Msk // Start of frame mask
1213#define GINTMSK_RXFLVLM_Pos (4U)
1214#define GINTMSK_RXFLVLM_Msk (0x1UL << GINTMSK_RXFLVLM_Pos) // 0x00000010
1215#define GINTMSK_RXFLVLM GINTMSK_RXFLVLM_Msk // Receive FIFO nonempty mask
1216#define GINTMSK_NPTXFEM_Pos (5U)
1217#define GINTMSK_NPTXFEM_Msk (0x1UL << GINTMSK_NPTXFEM_Pos) // 0x00000020
1218#define GINTMSK_NPTXFEM GINTMSK_NPTXFEM_Msk // Nonperiodic TxFIFO empty mask
1219#define GINTMSK_GINAKEFFM_Pos (6U)
1220#define GINTMSK_GINAKEFFM_Msk (0x1UL << GINTMSK_GINAKEFFM_Pos) // 0x00000040
1221#define GINTMSK_GINAKEFFM GINTMSK_GINAKEFFM_Msk // Global nonperiodic IN NAK effective mask
1222#define GINTMSK_GONAKEFFM_Pos (7U)
1223#define GINTMSK_GONAKEFFM_Msk (0x1UL << GINTMSK_GONAKEFFM_Pos) // 0x00000080
1224#define GINTMSK_GONAKEFFM GINTMSK_GONAKEFFM_Msk // Global OUT NAK effective mask
1225#define GINTMSK_ESUSPM_Pos (10U)
1226#define GINTMSK_ESUSPM_Msk (0x1UL << GINTMSK_ESUSPM_Pos) // 0x00000400
1227#define GINTMSK_ESUSPM GINTMSK_ESUSPM_Msk // Early suspend mask
1228#define GINTMSK_USBSUSPM_Pos (11U)
1229#define GINTMSK_USBSUSPM_Msk (0x1UL << GINTMSK_USBSUSPM_Pos) // 0x00000800
1230#define GINTMSK_USBSUSPM GINTMSK_USBSUSPM_Msk // USB suspend mask
1231#define GINTMSK_USBRST_Pos (12U)
1232#define GINTMSK_USBRST_Msk (0x1UL << GINTMSK_USBRST_Pos) // 0x00001000
1233#define GINTMSK_USBRST GINTMSK_USBRST_Msk // USB reset mask
1234#define GINTMSK_ENUMDNEM_Pos (13U)
1235#define GINTMSK_ENUMDNEM_Msk (0x1UL << GINTMSK_ENUMDNEM_Pos) // 0x00002000
1236#define GINTMSK_ENUMDNEM GINTMSK_ENUMDNEM_Msk // Enumeration done mask
1237#define GINTMSK_ISOODRPM_Pos (14U)
1238#define GINTMSK_ISOODRPM_Msk (0x1UL << GINTMSK_ISOODRPM_Pos) // 0x00004000
1239#define GINTMSK_ISOODRPM GINTMSK_ISOODRPM_Msk // Isochronous OUT packet dropped interrupt mask
1240#define GINTMSK_EOPFM_Pos (15U)
1241#define GINTMSK_EOPFM_Msk (0x1UL << GINTMSK_EOPFM_Pos) // 0x00008000
1242#define GINTMSK_EOPFM GINTMSK_EOPFM_Msk // End of periodic frame interrupt mask
1243#define GINTMSK_EPMISM_Pos (17U)
1244#define GINTMSK_EPMISM_Msk (0x1UL << GINTMSK_EPMISM_Pos) // 0x00020000
1245#define GINTMSK_EPMISM GINTMSK_EPMISM_Msk // Endpoint mismatch interrupt mask
1246#define GINTMSK_IEPINT_Pos (18U)
1247#define GINTMSK_IEPINT_Msk (0x1UL << GINTMSK_IEPINT_Pos) // 0x00040000
1248#define GINTMSK_IEPINT GINTMSK_IEPINT_Msk // IN endpoints interrupt mask
1249#define GINTMSK_OEPINT_Pos (19U)
1250#define GINTMSK_OEPINT_Msk (0x1UL << GINTMSK_OEPINT_Pos) // 0x00080000
1251#define GINTMSK_OEPINT GINTMSK_OEPINT_Msk // OUT endpoints interrupt mask
1252#define GINTMSK_IISOIXFRM_Pos (20U)
1253#define GINTMSK_IISOIXFRM_Msk (0x1UL << GINTMSK_IISOIXFRM_Pos) // 0x00100000
1254#define GINTMSK_IISOIXFRM GINTMSK_IISOIXFRM_Msk // Incomplete isochronous IN transfer mask
1255#define GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
1256#define GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) // 0x00200000
1257#define GINTMSK_PXFRM_IISOOXFRM GINTMSK_PXFRM_IISOOXFRM_Msk // Incomplete periodic transfer mask
1258#define GINTMSK_FSUSPM_Pos (22U)
1259#define GINTMSK_FSUSPM_Msk (0x1UL << GINTMSK_FSUSPM_Pos) // 0x00400000
1260#define GINTMSK_FSUSPM GINTMSK_FSUSPM_Msk // Data fetch suspended mask
1261#define GINTMSK_RSTDEM_Pos (23U)
1262#define GINTMSK_RSTDEM_Msk (0x1UL << GINTMSK_RSTDEM_Pos) // 0x00800000
1263#define GINTMSK_RSTDEM GINTMSK_RSTDEM_Msk // Reset detected interrupt mask
1264#define GINTMSK_PRTIM_Pos (24U)
1265#define GINTMSK_PRTIM_Msk (0x1UL << GINTMSK_PRTIM_Pos) // 0x01000000
1266#define GINTMSK_PRTIM GINTMSK_PRTIM_Msk // Host port interrupt mask
1267#define GINTMSK_HCIM_Pos (25U)
1268#define GINTMSK_HCIM_Msk (0x1UL << GINTMSK_HCIM_Pos) // 0x02000000
1269#define GINTMSK_HCIM GINTMSK_HCIM_Msk // Host channels interrupt mask
1270#define GINTMSK_PTXFEM_Pos (26U)
1271#define GINTMSK_PTXFEM_Msk (0x1UL << GINTMSK_PTXFEM_Pos) // 0x04000000
1272#define GINTMSK_PTXFEM GINTMSK_PTXFEM_Msk // Periodic TxFIFO empty mask
1273#define GINTMSK_LPMINTM_Pos (27U)
1274#define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) // 0x08000000
1275#define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk // LPM interrupt Mask
1276#define GINTMSK_CONIDSTSCHNGM_Pos (28U)
1277#define GINTMSK_CONIDSTSCHNGM_Msk (0x1UL << GINTMSK_CONIDSTSCHNGM_Pos) // 0x10000000
1278#define GINTMSK_CONIDSTSCHNGM GINTMSK_CONIDSTSCHNGM_Msk // Connector ID status change mask
1279#define GINTMSK_DISCINT_Pos (29U)
1280#define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) // 0x20000000
1281#define GINTMSK_DISCINT GINTMSK_DISCINT_Msk // Disconnect detected interrupt mask
1282#define GINTMSK_SRQIM_Pos (30U)
1283#define GINTMSK_SRQIM_Msk (0x1UL << GINTMSK_SRQIM_Pos) // 0x40000000
1284#define GINTMSK_SRQIM GINTMSK_SRQIM_Msk // Session request/new session detected interrupt mask
1285#define GINTMSK_WUIM_Pos (31U)
1286#define GINTMSK_WUIM_Msk (0x1UL << GINTMSK_WUIM_Pos) // 0x80000000
1287#define GINTMSK_WUIM GINTMSK_WUIM_Msk // Resume/remote wakeup detected interrupt mask
1288
1289/******************** Bit definition for DAINT register ********************/
1290#define DAINT_IEPINT_Pos (0U)
1291#define DAINT_IEPINT_Msk (0xFFFFUL << DAINT_IEPINT_Pos) // 0x0000FFFF
1292#define DAINT_IEPINT DAINT_IEPINT_Msk // IN endpoint interrupt bits
1293#define DAINT_OEPINT_Pos (16U)
1294#define DAINT_OEPINT_Msk (0xFFFFUL << DAINT_OEPINT_Pos) // 0xFFFF0000
1295#define DAINT_OEPINT DAINT_OEPINT_Msk // OUT endpoint interrupt bits
1296
1297/******************** Bit definition for HAINTMSK register ********************/
1298#define HAINTMSK_HAINTM_Pos (0U)
1299#define HAINTMSK_HAINTM_Msk (0xFFFFUL << HAINTMSK_HAINTM_Pos) // 0x0000FFFF
1300#define HAINTMSK_HAINTM HAINTMSK_HAINTM_Msk // Channel interrupt mask
1301
1302/******************** Bit definition for GRXSTSP register ********************/
1303#define GRXSTSP_EPNUM_Pos (0U)
1304#define GRXSTSP_EPNUM_Msk (0xFUL << GRXSTSP_EPNUM_Pos) // 0x0000000F
1305#define GRXSTSP_EPNUM GRXSTSP_EPNUM_Msk // IN EP interrupt mask bits
1306#define GRXSTSP_BCNT_Pos (4U)
1307#define GRXSTSP_BCNT_Msk (0x7FFUL << GRXSTSP_BCNT_Pos) // 0x00007FF0
1308#define GRXSTSP_BCNT GRXSTSP_BCNT_Msk // OUT EP interrupt mask bits
1309#define GRXSTSP_DPID_Pos (15U)
1310#define GRXSTSP_DPID_Msk (0x3UL << GRXSTSP_DPID_Pos) // 0x00018000
1311#define GRXSTSP_DPID GRXSTSP_DPID_Msk // OUT EP interrupt mask bits
1312#define GRXSTSP_PKTSTS_Pos (17U)
1313#define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) // 0x001E0000
1314#define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk // OUT EP interrupt mask bits
1315
1316/******************** Bit definition for DAINTMSK register ********************/
1317#define DAINTMSK_IEPM_Pos (0U)
1318#define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) // 0x0000FFFF
1319#define DAINTMSK_IEPM DAINTMSK_IEPM_Msk // IN EP interrupt mask bits
1320#define DAINTMSK_OEPM_Pos (16U)
1321#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) // 0xFFFF0000
1322#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk // OUT EP interrupt mask bits
1323
1324#define DAINT_SHIFT(_dir) ((_dir == TUSB_DIR_IN) ? 0 : 16)
1325
1326#if 0
1327/******************** Bit definition for OTG register ********************/
1328#define CHNUM_Pos (0U)
1329#define CHNUM_Msk (0xFUL << CHNUM_Pos) // 0x0000000F
1330#define CHNUM CHNUM_Msk // Channel number
1331#define CHNUM_0 (0x1UL << CHNUM_Pos) // 0x00000001
1332#define CHNUM_1 (0x2UL << CHNUM_Pos) // 0x00000002
1333#define CHNUM_2 (0x4UL << CHNUM_Pos) // 0x00000004
1334#define CHNUM_3 (0x8UL << CHNUM_Pos) // 0x00000008
1335#define BCNT_Pos (4U)
1336#define BCNT_Msk (0x7FFUL << BCNT_Pos) // 0x00007FF0
1337#define BCNT BCNT_Msk // Byte count
1338
1339#define DPID_Pos (15U)
1340#define DPID_Msk (0x3UL << DPID_Pos) // 0x00018000
1341#define DPID DPID_Msk // Data PID
1342#define DPID_0 (0x1UL << DPID_Pos) // 0x00008000
1343#define DPID_1 (0x2UL << DPID_Pos) // 0x00010000
1344
1345#define PKTSTS_Pos (17U)
1346#define PKTSTS_Msk (0xFUL << PKTSTS_Pos) // 0x001E0000
1347#define PKTSTS PKTSTS_Msk // Packet status
1348#define PKTSTS_0 (0x1UL << PKTSTS_Pos) // 0x00020000
1349#define PKTSTS_1 (0x2UL << PKTSTS_Pos) // 0x00040000
1350#define PKTSTS_2 (0x4UL << PKTSTS_Pos) // 0x00080000
1351#define PKTSTS_3 (0x8UL << PKTSTS_Pos) // 0x00100000
1352
1353#define EPNUM_Pos (0U)
1354#define EPNUM_Msk (0xFUL << EPNUM_Pos) // 0x0000000F
1355#define EPNUM EPNUM_Msk // Endpoint number
1356#define EPNUM_0 (0x1UL << EPNUM_Pos) // 0x00000001
1357#define EPNUM_1 (0x2UL << EPNUM_Pos) // 0x00000002
1358#define EPNUM_2 (0x4UL << EPNUM_Pos) // 0x00000004
1359#define EPNUM_3 (0x8UL << EPNUM_Pos) // 0x00000008
1360
1361#define FRMNUM_Pos (21U)
1362#define FRMNUM_Msk (0xFUL << FRMNUM_Pos) // 0x01E00000
1363#define FRMNUM FRMNUM_Msk // Frame number
1364#define FRMNUM_0 (0x1UL << FRMNUM_Pos) // 0x00200000
1365#define FRMNUM_1 (0x2UL << FRMNUM_Pos) // 0x00400000
1366#define FRMNUM_2 (0x4UL << FRMNUM_Pos) // 0x00800000
1367#define FRMNUM_3 (0x8UL << FRMNUM_Pos) // 0x01000000
1368#endif
1369
1370/******************** Bit definition for GRXFSIZ register ********************/
1371#define GRXFSIZ_RXFD_Pos (0U)
1372#define GRXFSIZ_RXFD_Msk (0xFFFFUL << GRXFSIZ_RXFD_Pos) // 0x0000FFFF
1373#define GRXFSIZ_RXFD GRXFSIZ_RXFD_Msk // RxFIFO depth
1374
1375/******************** Bit definition for DVBUSDIS register ********************/
1376#define DVBUSDIS_VBUSDT_Pos (0U)
1377#define DVBUSDIS_VBUSDT_Msk (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) // 0x0000FFFF
1378#define DVBUSDIS_VBUSDT DVBUSDIS_VBUSDT_Msk // Device VBUS discharge time
1379
1380/******************** Bit definition for OTG register ********************/
1381#define GNPTXFSIZ_NPTXFSA_Pos (0U)
1382#define GNPTXFSIZ_NPTXFSA_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos) // 0x0000FFFF
1383#define GNPTXFSIZ_NPTXFSA GNPTXFSIZ_NPTXFSA_Msk // Nonperiodic transmit RAM start address
1384#define GNPTXFSIZ_NPTXFD_Pos (16U)
1385#define GNPTXFSIZ_NPTXFD_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos) // 0xFFFF0000
1386#define GNPTXFSIZ_NPTXFD GNPTXFSIZ_NPTXFD_Msk // Nonperiodic TxFIFO depth
1387#define DIEPTXF0_TX0FSA_Pos (0U)
1388#define DIEPTXF0_TX0FSA_Msk (0xFFFFUL << DIEPTXF0_TX0FSA_Pos) // 0x0000FFFF
1389#define DIEPTXF0_TX0FSA DIEPTXF0_TX0FSA_Msk // Endpoint 0 transmit RAM start address
1390#define DIEPTXF0_TX0FD_Pos (16U)
1391#define DIEPTXF0_TX0FD_Msk (0xFFFFUL << DIEPTXF0_TX0FD_Pos) // 0xFFFF0000
1392#define DIEPTXF0_TX0FD DIEPTXF0_TX0FD_Msk // Endpoint 0 TxFIFO depth
1393
1394/******************** Bit definition for DVBUSPULSE register ********************/
1395#define DVBUSPULSE_DVBUSP_Pos (0U)
1396#define DVBUSPULSE_DVBUSP_Msk (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) // 0x00000FFF
1397#define DVBUSPULSE_DVBUSP DVBUSPULSE_DVBUSP_Msk // Device VBUS pulsing time
1398
1399/******************** Bit definition for GNPTXSTS register ********************/
1400#define GNPTXSTS_NPTXFSAV_Pos (0U)
1401#define GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) // 0x0000FFFF
1402#define GNPTXSTS_NPTXFSAV GNPTXSTS_NPTXFSAV_Msk // Nonperiodic TxFIFO space available
1403
1404#define GNPTXSTS_NPTQXSAV_Pos (16U)
1405#define GNPTXSTS_NPTQXSAV_Msk (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) // 0x00FF0000
1406#define GNPTXSTS_NPTQXSAV GNPTXSTS_NPTQXSAV_Msk // Nonperiodic transmit request queue space available
1407#define GNPTXSTS_NPTQXSAV_0 (0x01UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00010000
1408#define GNPTXSTS_NPTQXSAV_1 (0x02UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00020000
1409#define GNPTXSTS_NPTQXSAV_2 (0x04UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00040000
1410#define GNPTXSTS_NPTQXSAV_3 (0x08UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00080000
1411#define GNPTXSTS_NPTQXSAV_4 (0x10UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00100000
1412#define GNPTXSTS_NPTQXSAV_5 (0x20UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00200000
1413#define GNPTXSTS_NPTQXSAV_6 (0x40UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00400000
1414#define GNPTXSTS_NPTQXSAV_7 (0x80UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00800000
1415
1416#define GNPTXSTS_NPTXQTOP_Pos (24U)
1417#define GNPTXSTS_NPTXQTOP_Msk (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) // 0x7F000000
1418#define GNPTXSTS_NPTXQTOP GNPTXSTS_NPTXQTOP_Msk // Top of the nonperiodic transmit request queue
1419#define GNPTXSTS_NPTXQTOP_0 (0x01UL << GNPTXSTS_NPTXQTOP_Pos) // 0x01000000
1420#define GNPTXSTS_NPTXQTOP_1 (0x02UL << GNPTXSTS_NPTXQTOP_Pos) // 0x02000000
1421#define GNPTXSTS_NPTXQTOP_2 (0x04UL << GNPTXSTS_NPTXQTOP_Pos) // 0x04000000
1422#define GNPTXSTS_NPTXQTOP_3 (0x08UL << GNPTXSTS_NPTXQTOP_Pos) // 0x08000000
1423#define GNPTXSTS_NPTXQTOP_4 (0x10UL << GNPTXSTS_NPTXQTOP_Pos) // 0x10000000
1424#define GNPTXSTS_NPTXQTOP_5 (0x20UL << GNPTXSTS_NPTXQTOP_Pos) // 0x20000000
1425#define GNPTXSTS_NPTXQTOP_6 (0x40UL << GNPTXSTS_NPTXQTOP_Pos) // 0x40000000
1426
1427/******************** Bit definition for DTHRCTL register ********************/
1428#define DTHRCTL_NONISOTHREN_Pos (0U)
1429#define DTHRCTL_NONISOTHREN_Msk (0x1UL << DTHRCTL_NONISOTHREN_Pos) // 0x00000001
1430#define DTHRCTL_NONISOTHREN DTHRCTL_NONISOTHREN_Msk // Nonisochronous IN endpoints threshold enable
1431#define DTHRCTL_ISOTHREN_Pos (1U)
1432#define DTHRCTL_ISOTHREN_Msk (0x1UL << DTHRCTL_ISOTHREN_Pos) // 0x00000002
1433#define DTHRCTL_ISOTHREN DTHRCTL_ISOTHREN_Msk // ISO IN endpoint threshold enable
1434
1435#define DTHRCTL_TXTHRLEN_Pos (2U)
1436#define DTHRCTL_TXTHRLEN_Msk (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) // 0x000007FC
1437#define DTHRCTL_TXTHRLEN DTHRCTL_TXTHRLEN_Msk // Transmit threshold length
1438#define DTHRCTL_TXTHRLEN_0 (0x001UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000004
1439#define DTHRCTL_TXTHRLEN_1 (0x002UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000008
1440#define DTHRCTL_TXTHRLEN_2 (0x004UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000010
1441#define DTHRCTL_TXTHRLEN_3 (0x008UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000020
1442#define DTHRCTL_TXTHRLEN_4 (0x010UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000040
1443#define DTHRCTL_TXTHRLEN_5 (0x020UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000080
1444#define DTHRCTL_TXTHRLEN_6 (0x040UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000100
1445#define DTHRCTL_TXTHRLEN_7 (0x080UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000200
1446#define DTHRCTL_TXTHRLEN_8 (0x100UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000400
1447#define DTHRCTL_RXTHREN_Pos (16U)
1448#define DTHRCTL_RXTHREN_Msk (0x1UL << DTHRCTL_RXTHREN_Pos) // 0x00010000
1449#define DTHRCTL_RXTHREN DTHRCTL_RXTHREN_Msk // Receive threshold enable
1450
1451#define DTHRCTL_RXTHRLEN_Pos (17U)
1452#define DTHRCTL_RXTHRLEN_Msk (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) // 0x03FE0000
1453#define DTHRCTL_RXTHRLEN DTHRCTL_RXTHRLEN_Msk // Receive threshold length
1454#define DTHRCTL_RXTHRLEN_0 (0x001UL << DTHRCTL_RXTHRLEN_Pos) // 0x00020000
1455#define DTHRCTL_RXTHRLEN_1 (0x002UL << DTHRCTL_RXTHRLEN_Pos) // 0x00040000
1456#define DTHRCTL_RXTHRLEN_2 (0x004UL << DTHRCTL_RXTHRLEN_Pos) // 0x00080000
1457#define DTHRCTL_RXTHRLEN_3 (0x008UL << DTHRCTL_RXTHRLEN_Pos) // 0x00100000
1458#define DTHRCTL_RXTHRLEN_4 (0x010UL << DTHRCTL_RXTHRLEN_Pos) // 0x00200000
1459#define DTHRCTL_RXTHRLEN_5 (0x020UL << DTHRCTL_RXTHRLEN_Pos) // 0x00400000
1460#define DTHRCTL_RXTHRLEN_6 (0x040UL << DTHRCTL_RXTHRLEN_Pos) // 0x00800000
1461#define DTHRCTL_RXTHRLEN_7 (0x080UL << DTHRCTL_RXTHRLEN_Pos) // 0x01000000
1462#define DTHRCTL_RXTHRLEN_8 (0x100UL << DTHRCTL_RXTHRLEN_Pos) // 0x02000000
1463#define DTHRCTL_ARPEN_Pos (27U)
1464#define DTHRCTL_ARPEN_Msk (0x1UL << DTHRCTL_ARPEN_Pos) // 0x08000000
1465#define DTHRCTL_ARPEN DTHRCTL_ARPEN_Msk // Arbiter parking enable
1466
1467/******************** Bit definition for DIEPEMPMSK register ********************/
1468#define DIEPEMPMSK_INEPTXFEM_Pos (0U)
1469#define DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) // 0x0000FFFF
1470#define DIEPEMPMSK_INEPTXFEM DIEPEMPMSK_INEPTXFEM_Msk // IN EP Tx FIFO empty interrupt mask bits
1471
1472/******************** Bit definition for DEACHINT register ********************/
1473#define DEACHINT_IEP1INT_Pos (1U)
1474#define DEACHINT_IEP1INT_Msk (0x1UL << DEACHINT_IEP1INT_Pos) // 0x00000002
1475#define DEACHINT_IEP1INT DEACHINT_IEP1INT_Msk // IN endpoint 1interrupt bit
1476#define DEACHINT_OEP1INT_Pos (17U)
1477#define DEACHINT_OEP1INT_Msk (0x1UL << DEACHINT_OEP1INT_Pos) // 0x00020000
1478#define DEACHINT_OEP1INT DEACHINT_OEP1INT_Msk // OUT endpoint 1 interrupt bit
1479
1480/******************** Bit definition for GCCFG register ********************/
1481#define STM32_GCCFG_DCDET_Pos (0U)
1482#define STM32_GCCFG_DCDET_Msk (0x1UL << STM32_GCCFG_DCDET_Pos) // 0x00000001
1483#define STM32_GCCFG_DCDET STM32_GCCFG_DCDET_Msk // Data contact detection (DCD) status
1484
1485#define STM32_GCCFG_PDET_Pos (1U)
1486#define STM32_GCCFG_PDET_Msk (0x1UL << STM32_GCCFG_PDET_Pos) // 0x00000002
1487#define STM32_GCCFG_PDET STM32_GCCFG_PDET_Msk // Primary detection (PD) status
1488
1489#define STM32_GCCFG_SDET_Pos (2U)
1490#define STM32_GCCFG_SDET_Msk (0x1UL << STM32_GCCFG_SDET_Pos) // 0x00000004
1491#define STM32_GCCFG_SDET STM32_GCCFG_SDET_Msk // Secondary detection (SD) status
1492
1493#define STM32_GCCFG_PS2DET_Pos (3U)
1494#define STM32_GCCFG_PS2DET_Msk (0x1UL << STM32_GCCFG_PS2DET_Pos) // 0x00000008
1495#define STM32_GCCFG_PS2DET STM32_GCCFG_PS2DET_Msk // DM pull-up detection status
1496
1497#define STM32_GCCFG_PWRDWN_Pos (16U)
1498#define STM32_GCCFG_PWRDWN_Msk (0x1UL << STM32_GCCFG_PWRDWN_Pos) // 0x00010000
1499#define STM32_GCCFG_PWRDWN STM32_GCCFG_PWRDWN_Msk // Power down
1500
1501#define STM32_GCCFG_BCDEN_Pos (17U)
1502#define STM32_GCCFG_BCDEN_Msk (0x1UL << STM32_GCCFG_BCDEN_Pos) // 0x00020000
1503#define STM32_GCCFG_BCDEN STM32_GCCFG_BCDEN_Msk // Battery charging detector (BCD) enable
1504
1505#define STM32_GCCFG_DCDEN_Pos (18U)
1506#define STM32_GCCFG_DCDEN_Msk (0x1UL << STM32_GCCFG_DCDEN_Pos) // 0x00040000
1507#define STM32_GCCFG_DCDEN STM32_GCCFG_DCDEN_Msk // Data contact detection (DCD) mode enable*/
1508
1509#define STM32_GCCFG_PDEN_Pos (19U)
1510#define STM32_GCCFG_PDEN_Msk (0x1UL << STM32_GCCFG_PDEN_Pos) // 0x00080000
1511#define STM32_GCCFG_PDEN STM32_GCCFG_PDEN_Msk // Primary detection (PD) mode enable*/
1512
1513#define STM32_GCCFG_SDEN_Pos (20U)
1514#define STM32_GCCFG_SDEN_Msk (0x1UL << STM32_GCCFG_SDEN_Pos) // 0x00100000
1515#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (SD) mode enable
1516
1517#define STM32_GCCFG_VBDEN_Pos (21U)
1518#define STM32_GCCFG_VBDEN_Msk (0x1UL << STM32_GCCFG_VBDEN_Pos) // 0x00200000
1519#define STM32_GCCFG_VBDEN STM32_GCCFG_VBDEN_Msk // VBUS mode enable
1520
1521#define STM32_GCCFG_OTGIDEN_Pos (22U)
1522#define STM32_GCCFG_OTGIDEN_Msk (0x1UL << STM32_GCCFG_OTGIDEN_Pos) // 0x00400000
1523#define STM32_GCCFG_OTGIDEN STM32_GCCFG_OTGIDEN_Msk // OTG Id enable
1524
1525#define STM32_GCCFG_PHYHSEN_Pos (23U)
1526#define STM32_GCCFG_PHYHSEN_Msk (0x1UL << STM32_GCCFG_PHYHSEN_Pos) // 0x00800000
1527#define STM32_GCCFG_PHYHSEN STM32_GCCFG_PHYHSEN_Msk // HS PHY enable
1528
1529// TODO stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
1530//#define STM32_GCCFG_SDEN_Pos (22U)
1531//#define STM32_GCCFG_SDEN_Msk (0x1U << STM32_GCCFG_SDEN_Pos) // 0x00400000
1532//#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (PD) mode enable
1533
1534// TODO stm32u5a5 VBVALOVA is 23rd bit, conflict with PHYHSEN bit above
1535#define STM32_GCCFG_VBVALOVAL_Pos (23U)
1536#define STM32_GCCFG_VBVALOVAL_Msk (0x1U << STM32_GCCFG_VBVALOVAL_Pos) // 0x00800000
1537#define STM32_GCCFG_VBVALOVAL STM32_GCCFG_VBVALOVAL_Msk // Value of VBUSVLDEXT0 femtoPHY input
1538
1539#define STM32_GCCFG_VBVALEXTOEN_Pos (24U)
1540#define STM32_GCCFG_VBVALEXTOEN_Msk (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos) // 0x01000000
1541#define STM32_GCCFG_VBVALEXTOEN STM32_GCCFG_VBVALEXTOEN_Msk // Enables of VBUSVLDEXT0 femtoPHY input override
1542
1543#define STM32_GCCFG_PULLDOWNEN_Pos (25U)
1544#define STM32_GCCFG_PULLDOWNEN_Msk (0x1U << STM32_GCCFG_PULLDOWNEN_Pos) // 0x02000000
1545#define STM32_GCCFG_PULLDOWNEN STM32_GCCFG_PULLDOWNEN_Msk // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
1546
1547
1548/******************** Bit definition for DEACHINTMSK register ********************/
1549#define DEACHINTMSK_IEP1INTM_Pos (1U)
1550#define DEACHINTMSK_IEP1INTM_Msk (0x1UL << DEACHINTMSK_IEP1INTM_Pos) // 0x00000002
1551#define DEACHINTMSK_IEP1INTM DEACHINTMSK_IEP1INTM_Msk // IN Endpoint 1 interrupt mask bit
1552#define DEACHINTMSK_OEP1INTM_Pos (17U)
1553#define DEACHINTMSK_OEP1INTM_Msk (0x1UL << DEACHINTMSK_OEP1INTM_Pos) // 0x00020000
1554#define DEACHINTMSK_OEP1INTM DEACHINTMSK_OEP1INTM_Msk // OUT Endpoint 1 interrupt mask bit
1555
1556/******************** Bit definition for CID register ********************/
1557#define CID_PRODUCT_ID_Pos (0U)
1558#define CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) // 0xFFFFFFFF
1559#define CID_PRODUCT_ID CID_PRODUCT_ID_Msk // Product ID field
1560
1561/******************** Bit definition for GLPMCFG register ********************/
1562#define GLPMCFG_LPMEN_Pos (0U)
1563#define GLPMCFG_LPMEN_Msk (0x1UL << GLPMCFG_LPMEN_Pos) // 0x00000001
1564#define GLPMCFG_LPMEN GLPMCFG_LPMEN_Msk // LPM support enable
1565#define GLPMCFG_LPMACK_Pos (1U)
1566#define GLPMCFG_LPMACK_Msk (0x1UL << GLPMCFG_LPMACK_Pos) // 0x00000002
1567#define GLPMCFG_LPMACK GLPMCFG_LPMACK_Msk // LPM Token acknowledge enable
1568#define GLPMCFG_BESL_Pos (2U)
1569#define GLPMCFG_BESL_Msk (0xFUL << GLPMCFG_BESL_Pos) // 0x0000003C
1570#define GLPMCFG_BESL GLPMCFG_BESL_Msk // BESL value received with last ACKed LPM Token
1571#define GLPMCFG_REMWAKE_Pos (6U)
1572#define GLPMCFG_REMWAKE_Msk (0x1UL << GLPMCFG_REMWAKE_Pos) // 0x00000040
1573#define GLPMCFG_REMWAKE GLPMCFG_REMWAKE_Msk // bRemoteWake value received with last ACKed LPM Token
1574#define GLPMCFG_L1SSEN_Pos (7U)
1575#define GLPMCFG_L1SSEN_Msk (0x1UL << GLPMCFG_L1SSEN_Pos) // 0x00000080
1576#define GLPMCFG_L1SSEN GLPMCFG_L1SSEN_Msk // L1 shallow sleep enable
1577#define GLPMCFG_BESLTHRS_Pos (8U)
1578#define GLPMCFG_BESLTHRS_Msk (0xFUL << GLPMCFG_BESLTHRS_Pos) // 0x00000F00
1579#define GLPMCFG_BESLTHRS GLPMCFG_BESLTHRS_Msk // BESL threshold
1580#define GLPMCFG_L1DSEN_Pos (12U)
1581#define GLPMCFG_L1DSEN_Msk (0x1UL << GLPMCFG_L1DSEN_Pos) // 0x00001000
1582#define GLPMCFG_L1DSEN GLPMCFG_L1DSEN_Msk // L1 deep sleep enable
1583#define GLPMCFG_LPMRSP_Pos (13U)
1584#define GLPMCFG_LPMRSP_Msk (0x3UL << GLPMCFG_LPMRSP_Pos) // 0x00006000
1585#define GLPMCFG_LPMRSP GLPMCFG_LPMRSP_Msk // LPM response
1586#define GLPMCFG_SLPSTS_Pos (15U)
1587#define GLPMCFG_SLPSTS_Msk (0x1UL << GLPMCFG_SLPSTS_Pos) // 0x00008000
1588#define GLPMCFG_SLPSTS GLPMCFG_SLPSTS_Msk // Port sleep status
1589#define GLPMCFG_L1RSMOK_Pos (16U)
1590#define GLPMCFG_L1RSMOK_Msk (0x1UL << GLPMCFG_L1RSMOK_Pos) // 0x00010000
1591#define GLPMCFG_L1RSMOK GLPMCFG_L1RSMOK_Msk // Sleep State Resume OK
1592#define GLPMCFG_LPMCHIDX_Pos (17U)
1593#define GLPMCFG_LPMCHIDX_Msk (0xFUL << GLPMCFG_LPMCHIDX_Pos) // 0x001E0000
1594#define GLPMCFG_LPMCHIDX GLPMCFG_LPMCHIDX_Msk // LPM Channel Index
1595#define GLPMCFG_LPMRCNT_Pos (21U)
1596#define GLPMCFG_LPMRCNT_Msk (0x7UL << GLPMCFG_LPMRCNT_Pos) // 0x00E00000
1597#define GLPMCFG_LPMRCNT GLPMCFG_LPMRCNT_Msk // LPM retry count
1598#define GLPMCFG_SNDLPM_Pos (24U)
1599#define GLPMCFG_SNDLPM_Msk (0x1UL << GLPMCFG_SNDLPM_Pos) // 0x01000000
1600#define GLPMCFG_SNDLPM GLPMCFG_SNDLPM_Msk // Send LPM transaction
1601#define GLPMCFG_LPMRCNTSTS_Pos (25U)
1602#define GLPMCFG_LPMRCNTSTS_Msk (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) // 0x0E000000
1603#define GLPMCFG_LPMRCNTSTS GLPMCFG_LPMRCNTSTS_Msk // LPM retry count status
1604#define GLPMCFG_ENBESL_Pos (28U)
1605#define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) // 0x10000000
1606#define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk // Enable best effort service latency
1607
1608// GDFIFOCFG
1609#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
1610#define GDFIFOCFG_EPINFOBASE_SHIFT 16
1611#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
1612#define GDFIFOCFG_GDFIFOCFG_SHIFT 0
1613
1614/******************** Bit definition for DIEPEACHMSK1 register ********************/
1615#define DIEPEACHMSK1_XFRCM_Pos (0U)
1616#define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) // 0x00000001
1617#define DIEPEACHMSK1_XFRCM DIEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask
1618#define DIEPEACHMSK1_EPDM_Pos (1U)
1619#define DIEPEACHMSK1_EPDM_Msk (0x1UL << DIEPEACHMSK1_EPDM_Pos) // 0x00000002
1620#define DIEPEACHMSK1_EPDM DIEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask
1621#define DIEPEACHMSK1_TOM_Pos (3U)
1622#define DIEPEACHMSK1_TOM_Msk (0x1UL << DIEPEACHMSK1_TOM_Pos) // 0x00000008
1623#define DIEPEACHMSK1_TOM DIEPEACHMSK1_TOM_Msk // Timeout condition mask (nonisochronous endpoints)
1624#define DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
1625#define DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010
1626#define DIEPEACHMSK1_ITTXFEMSK DIEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask
1627#define DIEPEACHMSK1_INEPNMM_Pos (5U)
1628#define DIEPEACHMSK1_INEPNMM_Msk (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) // 0x00000020
1629#define DIEPEACHMSK1_INEPNMM DIEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask
1630#define DIEPEACHMSK1_INEPNEM_Pos (6U)
1631#define DIEPEACHMSK1_INEPNEM_Msk (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) // 0x00000040
1632#define DIEPEACHMSK1_INEPNEM DIEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask
1633#define DIEPEACHMSK1_TXFURM_Pos (8U)
1634#define DIEPEACHMSK1_TXFURM_Msk (0x1UL << DIEPEACHMSK1_TXFURM_Pos) // 0x00000100
1635#define DIEPEACHMSK1_TXFURM DIEPEACHMSK1_TXFURM_Msk // FIFO underrun mask
1636#define DIEPEACHMSK1_BIM_Pos (9U)
1637#define DIEPEACHMSK1_BIM_Msk (0x1UL << DIEPEACHMSK1_BIM_Pos) // 0x00000200
1638#define DIEPEACHMSK1_BIM DIEPEACHMSK1_BIM_Msk // BNA interrupt mask
1639#define DIEPEACHMSK1_NAKM_Pos (13U)
1640#define DIEPEACHMSK1_NAKM_Msk (0x1UL << DIEPEACHMSK1_NAKM_Pos) // 0x00002000
1641#define DIEPEACHMSK1_NAKM DIEPEACHMSK1_NAKM_Msk // NAK interrupt mask
1642
1643/******************** Bit definition for HPRT register ********************/
1644#define HPRT_CONN_STATUS_Pos (0U)
1645#define HPRT_CONN_STATUS_Msk (0x1UL << HPRT_CONN_STATUS_Pos) // 0x00000001
1646#define HPRT_CONN_STATUS HPRT_CONN_STATUS_Msk // Port connect status
1647#define HPRT_CONN_DETECT_Pos (1U)
1648#define HPRT_CONN_DETECT_Msk (0x1UL << HPRT_CONN_DETECT_Pos) // 0x00000002
1649#define HPRT_CONN_DETECT HPRT_CONN_DETECT_Msk // Port connect detected
1650#define HPRT_ENABLE_Pos (2U)
1651#define HPRT_ENABLE_Msk (0x1UL << HPRT_ENABLE_Pos) // 0x00000004
1652#define HPRT_ENABLE HPRT_ENABLE_Msk // Port enable
1653#define HPRT_ENABLE_CHANGE_Pos (3U)
1654#define HPRT_ENABLE_CHANGE_Msk (0x1UL << HPRT_ENABLE_CHANGE_Pos) // 0x00000008
1655#define HPRT_ENABLE_CHANGE HPRT_ENABLE_CHANGE_Msk // Port enable/disable change
1656#define HPRT_OVER_CURRENT_ACTIVE_Pos (4U)
1657#define HPRT_OVER_CURRENT_ACTIVE_Msk (0x1UL << HPRT_OVER_CURRENT_ACTIVE_Pos) // 0x00000010
1658#define HPRT_OVER_CURRENT_ACTIVE HPRT_OVER_CURRENT_ACTIVE_Msk // Port overcurrent active
1659#define HPRT_OVER_CURRENT_CHANGE_Pos (5U)
1660#define HPRT_OVER_CURRENT_CHANGE_Msk (0x1UL << HPRT_OVER_CURRENT_CHANGE_Pos) // 0x00000020
1661#define HPRT_OVER_CURRENT_CHANGE HPRT_OVER_CURRENT_CHANGE_Msk // Port overcurrent change
1662#define HPRT_RESUME_Pos (6U)
1663#define HPRT_RESUME_Msk (0x1UL << HPRT_RESUME_Pos) // 0x00000040
1664#define HPRT_RESUME HPRT_RESUME_Msk // Port resume
1665#define HPRT_SUSPEND_Pos (7U)
1666#define HPRT_SUSPEND_Msk (0x1UL << HPRT_SUSPEND_Pos) // 0x00000080
1667#define HPRT_SUSPEND HPRT_SUSPEND_Msk // Port suspend
1668#define HPRT_RESET_Pos (8U)
1669#define HPRT_RESET_Msk (0x1UL << HPRT_RESET_Pos) // 0x00000100
1670#define HPRT_RESET HPRT_RESET_Msk // Port reset
1671#define HPRT_LINE_STATUS_Pos (10U)
1672#define HPRT_LINE_STATUS_Msk (0x3UL << HPRT_LINE_STATUS_Pos) // 0x00000C00
1673#define HPRT_LINE_STATUS HPRT_LINE_STATUS_Msk // Port line status
1674#define HPRT_LINE_STATUS_0 (0x1UL << HPRT_LINE_STATUS_Pos) // 0x00000400
1675#define HPRT_LINE_STATUS_1 (0x2UL << HPRT_LINE_STATUS_Pos) // 0x00000800
1676#define HPRT_POWER_Pos (12U)
1677#define HPRT_POWER_Msk (0x1UL << HPRT_POWER_Pos) // 0x00001000
1678#define HPRT_POWER HPRT_POWER_Msk // Port power
1679#define HPRT_TEST_CONTROL_Pos (13U)
1680#define HPRT_TEST_CONTROL_Msk (0xFUL << HPRT_TEST_CONTROL_Pos) // 0x0001E000
1681#define HPRT_TEST_CONTROL HPRT_TEST_CONTROL_Msk // Port test control
1682#define HPRT_TEST_CONTROL_0 (0x1UL << HPRT_TEST_CONTROL_Pos) // 0x00002000
1683#define HPRT_TEST_CONTROL_1 (0x2UL << HPRT_TEST_CONTROL_Pos) // 0x00004000
1684#define HPRT_TEST_CONTROL_2 (0x4UL << HPRT_TEST_CONTROL_Pos) // 0x00008000
1685#define HPRT_TEST_CONTROL_3 (0x8UL << HPRT_TEST_CONTROL_Pos) // 0x00010000
1686#define HPRT_SPEED_Pos (17U)
1687#define HPRT_SPEED_Msk (0x3UL << HPRT_SPEED_Pos) // 0x00060000
1688#define HPRT_SPEED HPRT_SPEED_Msk // Port speed
1689#define HPRT_SPEED_0 (0x1UL << HPRT_SPEED_Pos) // 0x00020000
1690#define HPRT_SPEED_1 (0x2UL << HPRT_SPEED_Pos) // 0x00040000
1691
1692/******************** Bit definition for DOEPEACHMSK1 register ********************/
1693#define DOEPEACHMSK1_XFRCM_Pos (0U)
1694#define DOEPEACHMSK1_XFRCM_Msk (0x1UL << DOEPEACHMSK1_XFRCM_Pos) // 0x00000001
1695#define DOEPEACHMSK1_XFRCM DOEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask
1696#define DOEPEACHMSK1_EPDM_Pos (1U)
1697#define DOEPEACHMSK1_EPDM_Msk (0x1UL << DOEPEACHMSK1_EPDM_Pos) // 0x00000002
1698#define DOEPEACHMSK1_EPDM DOEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask
1699#define DOEPEACHMSK1_TOM_Pos (3U)
1700#define DOEPEACHMSK1_TOM_Msk (0x1UL << DOEPEACHMSK1_TOM_Pos) // 0x00000008
1701#define DOEPEACHMSK1_TOM DOEPEACHMSK1_TOM_Msk // Timeout condition mask
1702#define DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
1703#define DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010
1704#define DOEPEACHMSK1_ITTXFEMSK DOEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask
1705#define DOEPEACHMSK1_INEPNMM_Pos (5U)
1706#define DOEPEACHMSK1_INEPNMM_Msk (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) // 0x00000020
1707#define DOEPEACHMSK1_INEPNMM DOEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask
1708#define DOEPEACHMSK1_INEPNEM_Pos (6U)
1709#define DOEPEACHMSK1_INEPNEM_Msk (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) // 0x00000040
1710#define DOEPEACHMSK1_INEPNEM DOEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask
1711#define DOEPEACHMSK1_TXFURM_Pos (8U)
1712#define DOEPEACHMSK1_TXFURM_Msk (0x1UL << DOEPEACHMSK1_TXFURM_Pos) // 0x00000100
1713#define DOEPEACHMSK1_TXFURM DOEPEACHMSK1_TXFURM_Msk // OUT packet error mask
1714#define DOEPEACHMSK1_BIM_Pos (9U)
1715#define DOEPEACHMSK1_BIM_Msk (0x1UL << DOEPEACHMSK1_BIM_Pos) // 0x00000200
1716#define DOEPEACHMSK1_BIM DOEPEACHMSK1_BIM_Msk // BNA interrupt mask
1717#define DOEPEACHMSK1_BERRM_Pos (12U)
1718#define DOEPEACHMSK1_BERRM_Msk (0x1UL << DOEPEACHMSK1_BERRM_Pos) // 0x00001000
1719#define DOEPEACHMSK1_BERRM DOEPEACHMSK1_BERRM_Msk // Bubble error interrupt mask
1720#define DOEPEACHMSK1_NAKM_Pos (13U)
1721#define DOEPEACHMSK1_NAKM_Msk (0x1UL << DOEPEACHMSK1_NAKM_Pos) // 0x00002000
1722#define DOEPEACHMSK1_NAKM DOEPEACHMSK1_NAKM_Msk // NAK interrupt mask
1723#define DOEPEACHMSK1_NYETM_Pos (14U)
1724#define DOEPEACHMSK1_NYETM_Msk (0x1UL << DOEPEACHMSK1_NYETM_Pos) // 0x00004000
1725#define DOEPEACHMSK1_NYETM DOEPEACHMSK1_NYETM_Msk // NYET interrupt mask
1726
1727/******************** Bit definition for HPTXFSIZ register ********************/
1728#define HPTXFSIZ_PTXSA_Pos (0U)
1729#define HPTXFSIZ_PTXSA_Msk (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) // 0x0000FFFF
1730#define HPTXFSIZ_PTXSA HPTXFSIZ_PTXSA_Msk // Host periodic TxFIFO start address
1731#define HPTXFSIZ_PTXFD_Pos (16U)
1732#define HPTXFSIZ_PTXFD_Msk (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) // 0xFFFF0000
1733#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk // Host periodic TxFIFO depth
1734
1735/******************** Bit definition for DIEPCTL register ********************/
1736#define DIEPCTL_MPSIZ_Pos (0U)
1737#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) // 0x000007FF
1738#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk // Maximum packet size
1739#define DIEPCTL_USBAEP_Pos (15U)
1740#define DIEPCTL_USBAEP_Msk (0x1UL << DIEPCTL_USBAEP_Pos) // 0x00008000
1741#define DIEPCTL_USBAEP DIEPCTL_USBAEP_Msk // USB active endpoint
1742#define DIEPCTL_EONUM_DPID_Pos (16U)
1743#define DIEPCTL_EONUM_DPID_Msk (0x1UL << DIEPCTL_EONUM_DPID_Pos) // 0x00010000
1744#define DIEPCTL_EONUM_DPID DIEPCTL_EONUM_DPID_Msk // Even/odd frame
1745#define DIEPCTL_NAKSTS_Pos (17U)
1746#define DIEPCTL_NAKSTS_Msk (0x1UL << DIEPCTL_NAKSTS_Pos) // 0x00020000
1747#define DIEPCTL_NAKSTS DIEPCTL_NAKSTS_Msk // NAK status
1748
1749#define DIEPCTL_EPTYP_Pos (18U)
1750#define DIEPCTL_EPTYP_Msk (0x3UL << DIEPCTL_EPTYP_Pos) // 0x000C0000
1751#define DIEPCTL_EPTYP DIEPCTL_EPTYP_Msk // Endpoint type
1752#define DIEPCTL_EPTYP_0 (0x1UL << DIEPCTL_EPTYP_Pos) // 0x00040000
1753#define DIEPCTL_EPTYP_1 (0x2UL << DIEPCTL_EPTYP_Pos) // 0x00080000
1754#define DIEPCTL_STALL_Pos (21U)
1755#define DIEPCTL_STALL_Msk (0x1UL << DIEPCTL_STALL_Pos) // 0x00200000
1756#define DIEPCTL_STALL DIEPCTL_STALL_Msk // STALL handshake
1757
1758#define DIEPCTL_TXFNUM_Pos (22U)
1759#define DIEPCTL_TXFNUM_Msk (0xFUL << DIEPCTL_TXFNUM_Pos) // 0x03C00000
1760#define DIEPCTL_TXFNUM DIEPCTL_TXFNUM_Msk // TxFIFO number
1761#define DIEPCTL_TXFNUM_0 (0x1UL << DIEPCTL_TXFNUM_Pos) // 0x00400000
1762#define DIEPCTL_TXFNUM_1 (0x2UL << DIEPCTL_TXFNUM_Pos) // 0x00800000
1763#define DIEPCTL_TXFNUM_2 (0x4UL << DIEPCTL_TXFNUM_Pos) // 0x01000000
1764#define DIEPCTL_TXFNUM_3 (0x8UL << DIEPCTL_TXFNUM_Pos) // 0x02000000
1765#define DIEPCTL_CNAK_Pos (26U)
1766#define DIEPCTL_CNAK_Msk (0x1UL << DIEPCTL_CNAK_Pos) // 0x04000000
1767#define DIEPCTL_CNAK DIEPCTL_CNAK_Msk // Clear NAK
1768#define DIEPCTL_SNAK_Pos (27U)
1769#define DIEPCTL_SNAK_Msk (0x1UL << DIEPCTL_SNAK_Pos) // 0x08000000
1770#define DIEPCTL_SNAK DIEPCTL_SNAK_Msk // Set NAK
1771#define DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
1772#define DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000
1773#define DIEPCTL_SD0PID_SEVNFRM DIEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID
1774#define DIEPCTL_SODDFRM_Pos (29U)
1775#define DIEPCTL_SODDFRM_Msk (0x1UL << DIEPCTL_SODDFRM_Pos) // 0x20000000
1776#define DIEPCTL_SODDFRM DIEPCTL_SODDFRM_Msk // Set odd frame
1777#define DIEPCTL_EPDIS_Pos (30U)
1778#define DIEPCTL_EPDIS_Msk (0x1UL << DIEPCTL_EPDIS_Pos) // 0x40000000
1779#define DIEPCTL_EPDIS DIEPCTL_EPDIS_Msk // Endpoint disable
1780#define DIEPCTL_EPENA_Pos (31U)
1781#define DIEPCTL_EPENA_Msk (0x1UL << DIEPCTL_EPENA_Pos) // 0x80000000
1782#define DIEPCTL_EPENA DIEPCTL_EPENA_Msk // Endpoint enable
1783
1784/******************** Bit definition for HCCHAR register ********************/
1785#define HCCHAR_MPSIZ_Pos (0U)
1786#define HCCHAR_MPSIZ_Msk (0x7FFUL << HCCHAR_MPSIZ_Pos) // 0x000007FF
1787#define HCCHAR_MPSIZ HCCHAR_MPSIZ_Msk // Maximum packet size
1788
1789#define HCCHAR_EPNUM_Pos (11U)
1790#define HCCHAR_EPNUM_Msk (0xFUL << HCCHAR_EPNUM_Pos) // 0x00007800
1791#define HCCHAR_EPNUM HCCHAR_EPNUM_Msk // Endpoint number
1792#define HCCHAR_EPNUM_0 (0x1UL << HCCHAR_EPNUM_Pos) // 0x00000800
1793#define HCCHAR_EPNUM_1 (0x2UL << HCCHAR_EPNUM_Pos) // 0x00001000
1794#define HCCHAR_EPNUM_2 (0x4UL << HCCHAR_EPNUM_Pos) // 0x00002000
1795#define HCCHAR_EPNUM_3 (0x8UL << HCCHAR_EPNUM_Pos) // 0x00004000
1796#define HCCHAR_EPDIR_Pos (15U)
1797#define HCCHAR_EPDIR_Msk (0x1UL << HCCHAR_EPDIR_Pos) // 0x00008000
1798#define HCCHAR_EPDIR HCCHAR_EPDIR_Msk // Endpoint direction
1799#define HCCHAR_LSDEV_Pos (17U)
1800#define HCCHAR_LSDEV_Msk (0x1UL << HCCHAR_LSDEV_Pos) // 0x00020000
1801#define HCCHAR_LSDEV HCCHAR_LSDEV_Msk // Low-speed device
1802
1803#define HCCHAR_EPTYP_Pos (18U)
1804#define HCCHAR_EPTYP_Msk (0x3UL << HCCHAR_EPTYP_Pos) // 0x000C0000
1805#define HCCHAR_EPTYP HCCHAR_EPTYP_Msk // Endpoint type
1806#define HCCHAR_EPTYP_0 (0x1UL << HCCHAR_EPTYP_Pos) // 0x00040000
1807#define HCCHAR_EPTYP_1 (0x2UL << HCCHAR_EPTYP_Pos) // 0x00080000
1808
1809#define HCCHAR_MC_Pos (20U)
1810#define HCCHAR_MC_Msk (0x3UL << HCCHAR_MC_Pos) // 0x00300000
1811#define HCCHAR_MC HCCHAR_MC_Msk // Multi Count (MC) / Error Count (EC)
1812#define HCCHAR_MC_0 (0x1UL << HCCHAR_MC_Pos) // 0x00100000
1813#define HCCHAR_MC_1 (0x2UL << HCCHAR_MC_Pos) // 0x00200000
1814
1815#define HCCHAR_DAD_Pos (22U)
1816#define HCCHAR_DAD_Msk (0x7FUL << HCCHAR_DAD_Pos) // 0x1FC00000
1817#define HCCHAR_DAD HCCHAR_DAD_Msk // Device address
1818#define HCCHAR_DAD_0 (0x01UL << HCCHAR_DAD_Pos) // 0x00400000
1819#define HCCHAR_DAD_1 (0x02UL << HCCHAR_DAD_Pos) // 0x00800000
1820#define HCCHAR_DAD_2 (0x04UL << HCCHAR_DAD_Pos) // 0x01000000
1821#define HCCHAR_DAD_3 (0x08UL << HCCHAR_DAD_Pos) // 0x02000000
1822#define HCCHAR_DAD_4 (0x10UL << HCCHAR_DAD_Pos) // 0x04000000
1823#define HCCHAR_DAD_5 (0x20UL << HCCHAR_DAD_Pos) // 0x08000000
1824#define HCCHAR_DAD_6 (0x40UL << HCCHAR_DAD_Pos) // 0x10000000
1825#define HCCHAR_ODDFRM_Pos (29U)
1826#define HCCHAR_ODDFRM_Msk (0x1UL << HCCHAR_ODDFRM_Pos) // 0x20000000
1827#define HCCHAR_ODDFRM HCCHAR_ODDFRM_Msk // Odd frame
1828#define HCCHAR_CHDIS_Pos (30U)
1829#define HCCHAR_CHDIS_Msk (0x1UL << HCCHAR_CHDIS_Pos) // 0x40000000
1830#define HCCHAR_CHDIS HCCHAR_CHDIS_Msk // Channel disable
1831#define HCCHAR_CHENA_Pos (31U)
1832#define HCCHAR_CHENA_Msk (0x1UL << HCCHAR_CHENA_Pos) // 0x80000000
1833#define HCCHAR_CHENA HCCHAR_CHENA_Msk // Channel enable
1834
1835/******************** Bit definition for HCSPLT register ********************/
1836
1837#define HCSPLT_PRTADDR_Pos (0U)
1838#define HCSPLT_PRTADDR_Msk (0x7FUL << HCSPLT_PRTADDR_Pos) // 0x0000007F
1839#define HCSPLT_PRTADDR HCSPLT_PRTADDR_Msk // Port address
1840#define HCSPLT_PRTADDR_0 (0x01UL << HCSPLT_PRTADDR_Pos) // 0x00000001
1841#define HCSPLT_PRTADDR_1 (0x02UL << HCSPLT_PRTADDR_Pos) // 0x00000002
1842#define HCSPLT_PRTADDR_2 (0x04UL << HCSPLT_PRTADDR_Pos) // 0x00000004
1843#define HCSPLT_PRTADDR_3 (0x08UL << HCSPLT_PRTADDR_Pos) // 0x00000008
1844#define HCSPLT_PRTADDR_4 (0x10UL << HCSPLT_PRTADDR_Pos) // 0x00000010
1845#define HCSPLT_PRTADDR_5 (0x20UL << HCSPLT_PRTADDR_Pos) // 0x00000020
1846#define HCSPLT_PRTADDR_6 (0x40UL << HCSPLT_PRTADDR_Pos) // 0x00000040
1847
1848#define HCSPLT_HUBADDR_Pos (7U)
1849#define HCSPLT_HUBADDR_Msk (0x7FUL << HCSPLT_HUBADDR_Pos) // 0x00003F80
1850#define HCSPLT_HUBADDR HCSPLT_HUBADDR_Msk // Hub address
1851#define HCSPLT_HUBADDR_0 (0x01UL << HCSPLT_HUBADDR_Pos) // 0x00000080
1852#define HCSPLT_HUBADDR_1 (0x02UL << HCSPLT_HUBADDR_Pos) // 0x00000100
1853#define HCSPLT_HUBADDR_2 (0x04UL << HCSPLT_HUBADDR_Pos) // 0x00000200
1854#define HCSPLT_HUBADDR_3 (0x08UL << HCSPLT_HUBADDR_Pos) // 0x00000400
1855#define HCSPLT_HUBADDR_4 (0x10UL << HCSPLT_HUBADDR_Pos) // 0x00000800
1856#define HCSPLT_HUBADDR_5 (0x20UL << HCSPLT_HUBADDR_Pos) // 0x00001000
1857#define HCSPLT_HUBADDR_6 (0x40UL << HCSPLT_HUBADDR_Pos) // 0x00002000
1858
1859#define HCSPLT_XACTPOS_Pos (14U)
1860#define HCSPLT_XACTPOS_Msk (0x3UL << HCSPLT_XACTPOS_Pos) // 0x0000C000
1861#define HCSPLT_XACTPOS HCSPLT_XACTPOS_Msk // XACTPOS
1862#define HCSPLT_XACTPOS_0 (0x1UL << HCSPLT_XACTPOS_Pos) // 0x00004000
1863#define HCSPLT_XACTPOS_1 (0x2UL << HCSPLT_XACTPOS_Pos) // 0x00008000
1864#define HCSPLT_COMPLSPLT_Pos (16U)
1865#define HCSPLT_COMPLSPLT_Msk (0x1UL << HCSPLT_COMPLSPLT_Pos) // 0x00010000
1866#define HCSPLT_COMPLSPLT HCSPLT_COMPLSPLT_Msk // Do complete split
1867#define HCSPLT_SPLITEN_Pos (31U)
1868#define HCSPLT_SPLITEN_Msk (0x1UL << HCSPLT_SPLITEN_Pos) // 0x80000000
1869#define HCSPLT_SPLITEN HCSPLT_SPLITEN_Msk // Split enable
1870
1871/******************** Bit definition for HCINT register ********************/
1872#define HCINT_XFER_COMPLETE_Pos (0U)
1873#define HCINT_XFER_COMPLETE_Msk (0x1UL << HCINT_XFER_COMPLETE_Pos) // 0x00000001
1874#define HCINT_XFER_COMPLETE HCINT_XFER_COMPLETE_Msk // Transfer completed
1875#define HCINT_HALTED_Pos (1U)
1876#define HCINT_HALTED_Msk (0x1UL << HCINT_HALTED_Pos) // 0x00000002
1877#define HCINT_HALTED HCINT_HALTED_Msk // Channel halted
1878#define HCINT_AHB_ERR_Pos (2U)
1879#define HCINT_AHB_ERR_Msk (0x1UL << HCINT_AHB_ERR_Pos) // 0x00000004
1880#define HCINT_AHB_ERR HCINT_AHB_ERR_Msk // AHB error
1881#define HCINT_STALL_Pos (3U)
1882#define HCINT_STALL_Msk (0x1UL << HCINT_STALL_Pos) // 0x00000008
1883#define HCINT_STALL HCINT_STALL_Msk // STALL response received interrupt
1884#define HCINT_NAK_Pos (4U)
1885#define HCINT_NAK_Msk (0x1UL << HCINT_NAK_Pos) // 0x00000010
1886#define HCINT_NAK HCINT_NAK_Msk // NAK response received interrupt
1887#define HCINT_ACK_Pos (5U)
1888#define HCINT_ACK_Msk (0x1UL << HCINT_ACK_Pos) // 0x00000020
1889#define HCINT_ACK HCINT_ACK_Msk // ACK response received/transmitted interrupt
1890#define HCINT_NYET_Pos (6U)
1891#define HCINT_NYET_Msk (0x1UL << HCINT_NYET_Pos) // 0x00000040
1892#define HCINT_NYET HCINT_NYET_Msk // Response received interrupt
1893#define HCINT_XACT_ERR_Pos (7U)
1894#define HCINT_XACT_ERR_Msk (0x1UL << HCINT_XACT_ERR_Pos) // 0x00000080
1895#define HCINT_XACT_ERR HCINT_XACT_ERR_Msk // Transaction error
1896#define HCINT_BABBLE_ERR_Pos (8U)
1897#define HCINT_BABBLE_ERR_Msk (0x1UL << HCINT_BABBLE_ERR_Pos) // 0x00000100
1898#define HCINT_BABBLE_ERR HCINT_BABBLE_ERR_Msk // Babble error
1899#define HCINT_FARME_OVERRUN_Pos (9U)
1900#define HCINT_FARME_OVERRUN_Msk (0x1UL << HCINT_FARME_OVERRUN_Pos) // 0x00000200
1901#define HCINT_FARME_OVERRUN HCINT_FARME_OVERRUN_Msk // Frame overrun
1902#define HCINT_DATATOGGLE_ERR_Pos (10U)
1903#define HCINT_DATATOGGLE_ERR_Msk (0x1UL << HCINT_DATATOGGLE_ERR_Pos) // 0x00000400
1904#define HCINT_DATATOGGLE_ERR HCINT_DATATOGGLE_ERR_Msk // Data toggle error
1905#define HCINT_BUFFER_NA_Pos (11U)
1906#define HCINT_BUFFER_NA_Msk (0x1UL << HCINT_BUFFER_NA_Pos) // 0x00000800
1907#define HCINT_BUFFER_NA HCINT_BUFFER_NA_Msk // Buffer not available interrupt
1908#define HCINT_XCS_XACT_ERR_Pos (12U)
1909#define HCINT_XCS_XACT_ERR_Msk (0x1UL << HCINT_XCS_XACT_ERR_Pos) // 0x00001000
1910#define HCINT_XCS_XACT_ERR HCINT_XCS_XACT_ERR_Msk // Excessive transaction error
1911#define HCINT_DESC_ROLLOVER_Pos (13U)
1912#define HCINT_DESC_ROLLOVER_Msk (0x1UL << HCINT_DESC_ROLLOVER_Pos) // 0x00002000
1913#define HCINT_DESC_ROLLOVER HCINT_DESC_ROLLOVER_Msk // Descriptor rollover
1914
1915/******************** Bit definition for DIEPINT register ********************/
1916#define DIEPINT_XFRC_Pos (0U)
1917#define DIEPINT_XFRC_Msk (0x1UL << DIEPINT_XFRC_Pos) // 0x00000001
1918#define DIEPINT_XFRC DIEPINT_XFRC_Msk // Transfer completed interrupt
1919#define DIEPINT_EPDISD_Pos (1U)
1920#define DIEPINT_EPDISD_Msk (0x1UL << DIEPINT_EPDISD_Pos) // 0x00000002
1921#define DIEPINT_EPDISD DIEPINT_EPDISD_Msk // Endpoint disabled interrupt
1922#define DIEPINT_AHBERR_Pos (2U)
1923#define DIEPINT_AHBERR_Msk (0x1UL << DIEPINT_AHBERR_Pos) // 0x00000004
1924#define DIEPINT_AHBERR DIEPINT_AHBERR_Msk // AHB Error (AHBErr) during an IN transaction
1925#define DIEPINT_TOC_Pos (3U)
1926#define DIEPINT_TOC_Msk (0x1UL << DIEPINT_TOC_Pos) // 0x00000008
1927#define DIEPINT_TOC DIEPINT_TOC_Msk // Timeout condition
1928#define DIEPINT_ITTXFE_Pos (4U)
1929#define DIEPINT_ITTXFE_Msk (0x1UL << DIEPINT_ITTXFE_Pos) // 0x00000010
1930#define DIEPINT_ITTXFE DIEPINT_ITTXFE_Msk // IN token received when TxFIFO is empty
1931#define DIEPINT_INEPNM_Pos (5U)
1932#define DIEPINT_INEPNM_Msk (0x1UL << DIEPINT_INEPNM_Pos) // 0x00000020
1933#define DIEPINT_INEPNM DIEPINT_INEPNM_Msk // IN token received with EP mismatch
1934#define DIEPINT_INEPNE_Pos (6U)
1935#define DIEPINT_INEPNE_Msk (0x1UL << DIEPINT_INEPNE_Pos) // 0x00000040
1936#define DIEPINT_INEPNE DIEPINT_INEPNE_Msk // IN endpoint NAK effective
1937#define DIEPINT_TXFE_Pos (7U)
1938#define DIEPINT_TXFE_Msk (0x1UL << DIEPINT_TXFE_Pos) // 0x00000080
1939#define DIEPINT_TXFE DIEPINT_TXFE_Msk // Transmit FIFO empty
1940#define DIEPINT_TXFIFOUDRN_Pos (8U)
1941#define DIEPINT_TXFIFOUDRN_Msk (0x1UL << DIEPINT_TXFIFOUDRN_Pos) // 0x00000100
1942#define DIEPINT_TXFIFOUDRN DIEPINT_TXFIFOUDRN_Msk // Transmit Fifo Underrun
1943#define DIEPINT_BNA_Pos (9U)
1944#define DIEPINT_BNA_Msk (0x1UL << DIEPINT_BNA_Pos) // 0x00000200
1945#define DIEPINT_BNA DIEPINT_BNA_Msk // Buffer not available interrupt
1946#define DIEPINT_PKTDRPSTS_Pos (11U)
1947#define DIEPINT_PKTDRPSTS_Msk (0x1UL << DIEPINT_PKTDRPSTS_Pos) // 0x00000800
1948#define DIEPINT_PKTDRPSTS DIEPINT_PKTDRPSTS_Msk // Packet dropped status
1949#define DIEPINT_BERR_Pos (12U)
1950#define DIEPINT_BERR_Msk (0x1UL << DIEPINT_BERR_Pos) // 0x00001000
1951#define DIEPINT_BERR DIEPINT_BERR_Msk // Babble error interrupt
1952#define DIEPINT_NAK_Pos (13U)
1953#define DIEPINT_NAK_Msk (0x1UL << DIEPINT_NAK_Pos) // 0x00002000
1954#define DIEPINT_NAK DIEPINT_NAK_Msk // NAK interrupt
1955
1956/******************** Bit definition for DIEPTSIZ register ********************/
1957
1958#define DIEPTSIZ_XFRSIZ_Pos (0U)
1959#define DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF
1960#define DIEPTSIZ_XFRSIZ DIEPTSIZ_XFRSIZ_Msk // Transfer size
1961#define DIEPTSIZ_PKTCNT_Pos (19U)
1962#define DIEPTSIZ_PKTCNT_Msk (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) // 0x1FF80000
1963#define DIEPTSIZ_PKTCNT DIEPTSIZ_PKTCNT_Msk // Packet count
1964#define DIEPTSIZ_MULCNT_Pos (29U)
1965#define DIEPTSIZ_MULCNT_Msk (0x3UL << DIEPTSIZ_MULCNT_Pos) // 0x60000000
1966#define DIEPTSIZ_MULCNT DIEPTSIZ_MULCNT_Msk // Packet count
1967 /******************** Bit definition for HCTSIZ register ********************/
1968#define HCTSIZ_XFRSIZ_Pos (0U)
1969#define HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) // 0x0007FFFF
1970#define HCTSIZ_XFRSIZ HCTSIZ_XFRSIZ_Msk // Transfer size
1971#define HCTSIZ_PKTCNT_Pos (19U)
1972#define HCTSIZ_PKTCNT_Msk (0x3FFUL << HCTSIZ_PKTCNT_Pos) // 0x1FF80000
1973#define HCTSIZ_PKTCNT HCTSIZ_PKTCNT_Msk // Packet count
1974#define HCTSIZ_DOPING_Pos (31U)
1975#define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) // 0x80000000
1976#define HCTSIZ_DOPING HCTSIZ_DOPING_Msk // Do PING
1977#define HCTSIZ_PID_Pos (29U)
1978#define HCTSIZ_PID_Msk (0x3UL << HCTSIZ_PID_Pos) // 0x60000000
1979#define HCTSIZ_PID HCTSIZ_PID_Msk // Data PID
1980
1981/******************** Bit definition for DIEPDMA register ********************/
1982#define DIEPDMA_DMAADDR_Pos (0U)
1983#define DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) // 0xFFFFFFFF
1984#define DIEPDMA_DMAADDR DIEPDMA_DMAADDR_Msk // DMA address
1985
1986/******************** Bit definition for HCDMA register ********************/
1987#define HCDMA_DMAADDR_Pos (0U)
1988#define HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) // 0xFFFFFFFF
1989#define HCDMA_DMAADDR HCDMA_DMAADDR_Msk // DMA address
1990
1991 /******************** Bit definition for DTXFSTS register ********************/
1992#define DTXFSTS_INEPTFSAV_Pos (0U)
1993#define DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) // 0x0000FFFF
1994#define DTXFSTS_INEPTFSAV DTXFSTS_INEPTFSAV_Msk // IN endpoint TxFIFO space available
1995
1996 /******************** Bit definition for DIEPTXF register ********************/
1997#define DIEPTXF_INEPTXSA_Pos (0U)
1998#define DIEPTXF_INEPTXSA_Msk (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) // 0x0000FFFF
1999#define DIEPTXF_INEPTXSA DIEPTXF_INEPTXSA_Msk // IN endpoint FIFOx transmit RAM start address
2000#define DIEPTXF_INEPTXFD_Pos (16U)
2001#define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) // 0xFFFF0000
2002#define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk // IN endpoint TxFIFO depth
2003
2004
2005/******************** Bit definition for Common EPCTL register ********************/
2006#define EPCTL_MPSIZ_Pos (0U)
2007#define EPCTL_MPSIZ_Msk (0x7FFUL << EPCTL_MPSIZ_Pos) // 0x000007FF
2008#define EPCTL_MPSIZ EPCTL_MPSIZ_Msk // Maximum packet size //Bit 1
2009#define EPCTL_USBAEP_Pos (15U)
2010#define EPCTL_USBAEP_Msk (0x1UL << EPCTL_USBAEP_Pos) // 0x00008000
2011#define EPCTL_USBAEP EPCTL_USBAEP_Msk // USB active endpoint
2012#define EPCTL_NAKSTS_Pos (17U)
2013#define EPCTL_NAKSTS_Msk (0x1UL << EPCTL_NAKSTS_Pos) // 0x00020000
2014#define EPCTL_NAKSTS EPCTL_NAKSTS_Msk // NAK status
2015#define EPCTL_EPTYP_Pos (18U)
2016#define EPCTL_EPTYP_Msk (0x3UL << EPCTL_EPTYP_Pos) // 0x000C0000
2017#define EPCTL_EPTYP EPCTL_EPTYP_Msk // Endpoint type
2018#define EPCTL_EPTYP_0 (0x1UL << EPCTL_EPTYP_Pos) // 0x00040000
2019#define EPCTL_EPTYP_1 (0x2UL << EPCTL_EPTYP_Pos) // 0x00080000
2020#define EPCTL_SNPM EPCTL_SNPM_Msk // Snoop mode
2021#define EPCTL_STALL_Pos (21U)
2022#define EPCTL_STALL_Msk (0x1UL << EPCTL_STALL_Pos) // 0x00200000
2023#define EPCTL_STALL EPCTL_STALL_Msk // STALL handshake
2024#define EPCTL_CNAK_Pos (26U)
2025#define EPCTL_CNAK_Msk (0x1UL << EPCTL_CNAK_Pos) // 0x04000000
2026#define EPCTL_CNAK EPCTL_CNAK_Msk // Clear NAK
2027#define EPCTL_SNAK_Pos (27U)
2028#define EPCTL_SNAK_Msk (0x1UL << EPCTL_SNAK_Pos) // 0x08000000
2029#define EPCTL_SNAK EPCTL_SNAK_Msk // Set NAK
2030#define EPCTL_SD0PID_SEVNFRM_Pos (28U)
2031#define EPCTL_SD0PID_SEVNFRM_Msk (0x1UL << EPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000
2032#define EPCTL_SD0PID_SEVNFRM EPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID
2033#define EPCTL_SODDFRM_Pos (29U)
2034#define EPCTL_SODDFRM_Msk (0x1UL << EPCTL_SODDFRM_Pos) // 0x20000000
2035#define EPCTL_SODDFRM EPCTL_SODDFRM_Msk // Set odd frame
2036#define EPCTL_EPDIS_Pos (30U)
2037#define EPCTL_EPDIS_Msk (0x1UL << EPCTL_EPDIS_Pos) // 0x40000000
2038#define EPCTL_EPDIS EPCTL_EPDIS_Msk // Endpoint disable
2039#define EPCTL_EPENA_Pos (31U)
2040#define EPCTL_EPENA_Msk (0x1UL << EPCTL_EPENA_Pos) // 0x80000000
2041#define EPCTL_EPENA EPCTL_EPENA_Msk // Endpoint enable
2042
2043/******************** Bit definition for DOEPCTL register ********************/
2044#define DOEPCTL_MPSIZ_Pos (0U)
2045#define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF
2046#define DOEPCTL_MPSIZ DOEPCTL_MPSIZ_Msk // Maximum packet size //Bit 1
2047#define DOEPCTL_USBAEP_Pos (15U)
2048#define DOEPCTL_USBAEP_Msk (0x1UL << DOEPCTL_USBAEP_Pos) // 0x00008000
2049#define DOEPCTL_USBAEP DOEPCTL_USBAEP_Msk // USB active endpoint
2050#define DOEPCTL_NAKSTS_Pos (17U)
2051#define DOEPCTL_NAKSTS_Msk (0x1UL << DOEPCTL_NAKSTS_Pos) // 0x00020000
2052#define DOEPCTL_NAKSTS DOEPCTL_NAKSTS_Msk // NAK status
2053#define DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
2054#define DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000
2055#define DOEPCTL_SD0PID_SEVNFRM DOEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID
2056#define DOEPCTL_SODDFRM_Pos (29U)
2057#define DOEPCTL_SODDFRM_Msk (0x1UL << DOEPCTL_SODDFRM_Pos) // 0x20000000
2058#define DOEPCTL_SODDFRM DOEPCTL_SODDFRM_Msk // Set odd frame
2059#define DOEPCTL_EPTYP_Pos (18U)
2060#define DOEPCTL_EPTYP_Msk (0x3UL << DOEPCTL_EPTYP_Pos) // 0x000C0000
2061#define DOEPCTL_EPTYP DOEPCTL_EPTYP_Msk // Endpoint type
2062#define DOEPCTL_EPTYP_0 (0x1UL << DOEPCTL_EPTYP_Pos) // 0x00040000
2063#define DOEPCTL_EPTYP_1 (0x2UL << DOEPCTL_EPTYP_Pos) // 0x00080000
2064#define DOEPCTL_SNPM_Pos (20U)
2065#define DOEPCTL_SNPM_Msk (0x1UL << DOEPCTL_SNPM_Pos) // 0x00100000
2066#define DOEPCTL_SNPM DOEPCTL_SNPM_Msk // Snoop mode
2067#define DOEPCTL_STALL_Pos (21U)
2068#define DOEPCTL_STALL_Msk (0x1UL << DOEPCTL_STALL_Pos) // 0x00200000
2069#define DOEPCTL_STALL DOEPCTL_STALL_Msk // STALL handshake
2070#define DOEPCTL_CNAK_Pos (26U)
2071#define DOEPCTL_CNAK_Msk (0x1UL << DOEPCTL_CNAK_Pos) // 0x04000000
2072#define DOEPCTL_CNAK DOEPCTL_CNAK_Msk // Clear NAK
2073#define DOEPCTL_SNAK_Pos (27U)
2074#define DOEPCTL_SNAK_Msk (0x1UL << DOEPCTL_SNAK_Pos) // 0x08000000
2075#define DOEPCTL_SNAK DOEPCTL_SNAK_Msk // Set NAK
2076#define DOEPCTL_EPDIS_Pos (30U)
2077#define DOEPCTL_EPDIS_Msk (0x1UL << DOEPCTL_EPDIS_Pos) // 0x40000000
2078#define DOEPCTL_EPDIS DOEPCTL_EPDIS_Msk // Endpoint disable
2079#define DOEPCTL_EPENA_Pos (31U)
2080#define DOEPCTL_EPENA_Msk (0x1UL << DOEPCTL_EPENA_Pos) // 0x80000000
2081#define DOEPCTL_EPENA DOEPCTL_EPENA_Msk // Endpoint enable
2082
2083/******************** Bit definition for DOEPINT register ********************/
2084#define DOEPINT_XFRC_Pos (0U)
2085#define DOEPINT_XFRC_Msk (0x1UL << DOEPINT_XFRC_Pos) // 0x00000001
2086#define DOEPINT_XFRC DOEPINT_XFRC_Msk // Transfer completed interrupt
2087#define DOEPINT_EPDISD_Pos (1U)
2088#define DOEPINT_EPDISD_Msk (0x1UL << DOEPINT_EPDISD_Pos) // 0x00000002
2089#define DOEPINT_EPDISD DOEPINT_EPDISD_Msk // Endpoint disabled interrupt
2090#define DOEPINT_AHBERR_Pos (2U)
2091#define DOEPINT_AHBERR_Msk (0x1UL << DOEPINT_AHBERR_Pos) // 0x00000004
2092#define DOEPINT_AHBERR DOEPINT_AHBERR_Msk // AHB Error (AHBErr) during an OUT transaction
2093
2094#define DOEPINT_SETUP_Pos (3U)
2095#define DOEPINT_SETUP_Msk (0x1UL << DOEPINT_SETUP_Pos) // 0x00000008
2096#define DOEPINT_SETUP DOEPINT_SETUP_Msk // SETUP phase done
2097
2098#define DOEPINT_OTEPDIS_Pos (4U)
2099#define DOEPINT_OTEPDIS_Msk (0x1UL << DOEPINT_OTEPDIS_Pos) // 0x00000010
2100#define DOEPINT_OTEPDIS DOEPINT_OTEPDIS_Msk // OUT token received when endpoint disabled
2101
2102#define DOEPINT_STSPHSRX_Pos (5U)
2103#define DOEPINT_STSPHSRX_Msk (0x1UL << DOEPINT_STSPHSRX_Pos) // 0x00000020
2104#define DOEPINT_STSPHSRX DOEPINT_STSPHSRX_Msk // Status Phase Received For Control Write
2105
2106#define DOEPINT_B2BSTUP_Pos (6U)
2107#define DOEPINT_B2BSTUP_Msk (0x1UL << DOEPINT_B2BSTUP_Pos) // 0x00000040
2108#define DOEPINT_B2BSTUP DOEPINT_B2BSTUP_Msk // Back-to-back SETUP packets received
2109#define DOEPINT_OUTPKTERR_Pos (8U)
2110#define DOEPINT_OUTPKTERR_Msk (0x1UL << DOEPINT_OUTPKTERR_Pos) // 0x00000100
2111#define DOEPINT_OUTPKTERR DOEPINT_OUTPKTERR_Msk // OUT packet error
2112#define DOEPINT_NAK_Pos (13U)
2113#define DOEPINT_NAK_Msk (0x1UL << DOEPINT_NAK_Pos) // 0x00002000
2114#define DOEPINT_NAK DOEPINT_NAK_Msk // NAK Packet is transmitted by the device
2115#define DOEPINT_NYET_Pos (14U)
2116#define DOEPINT_NYET_Msk (0x1UL << DOEPINT_NYET_Pos) // 0x00004000
2117#define DOEPINT_NYET DOEPINT_NYET_Msk // NYET interrupt
2118
2119#define DOEPINT_STPKTRX_Pos (15U)
2120#define DOEPINT_STPKTRX_Msk (0x1UL << DOEPINT_STPKTRX_Pos) // 0x00008000
2121#define DOEPINT_STPKTRX DOEPINT_STPKTRX_Msk // Setup Packet Received
2122
2123/******************** Bit definition for DOEPTSIZ register ********************/
2124#define DOEPTSIZ_XFRSIZ_Pos (0U)
2125#define DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF
2126#define DOEPTSIZ_XFRSIZ DOEPTSIZ_XFRSIZ_Msk // Transfer size
2127#define DOEPTSIZ_PKTCNT_Pos (19U)
2128#define DOEPTSIZ_PKTCNT_Msk (0x3FFUL << DOEPTSIZ_PKTCNT_Pos) // 0x1FF80000
2129#define DOEPTSIZ_PKTCNT DOEPTSIZ_PKTCNT_Msk // Packet count
2130
2131#define DOEPTSIZ_STUPCNT_Pos (29U)
2132#define DOEPTSIZ_STUPCNT_Msk (0x3UL << DOEPTSIZ_STUPCNT_Pos) // 0x60000000
2133#define DOEPTSIZ_STUPCNT DOEPTSIZ_STUPCNT_Msk // SETUP packet count
2134#define DOEPTSIZ_STUPCNT_0 (0x1UL << DOEPTSIZ_STUPCNT_Pos) // 0x20000000
2135#define DOEPTSIZ_STUPCNT_1 (0x2UL << DOEPTSIZ_STUPCNT_Pos) // 0x40000000
2136
2137/******************** Bit definition for PCGCTL register ********************/
2138#define PCGCCTL_IF_DEV_MODE TU_BIT(31)
2139#define PCGCCTL_P2HD_PRT_SPD_MASK (0x3ul << 29)
2140#define PCGCCTL_P2HD_PRT_SPD_SHIFT 29
2141#define PCGCCTL_P2HD_DEV_ENUM_SPD_MASK (0x3ul << 27)
2142#define PCGCCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
2143#define PCGCCTL_MAC_DEV_ADDR_MASK (0x7ful << 20)
2144#define PCGCCTL_MAC_DEV_ADDR_SHIFT 20
2145#define PCGCCTL_MAX_TERMSEL TU_BIT(19)
2146#define PCGCCTL_MAX_XCVRSELECT_MASK (0x3ul << 17)
2147#define PCGCCTL_MAX_XCVRSELECT_SHIFT 17
2148#define PCGCCTL_PORT_POWER TU_BIT(16)
2149#define PCGCCTL_PRT_CLK_SEL_MASK (0x3ul << 14)
2150#define PCGCCTL_PRT_CLK_SEL_SHIFT 14
2151#define PCGCCTL_ESS_REG_RESTORED TU_BIT(13)
2152#define PCGCCTL_EXTND_HIBER_SWITCH TU_BIT(12)
2153#define PCGCCTL_EXTND_HIBER_PWRCLMP TU_BIT(11)
2154#define PCGCCTL_ENBL_EXTND_HIBER TU_BIT(10)
2155#define PCGCCTL_RESTOREMODE TU_BIT(9)
2156#define PCGCCTL_RESETAFTSUSP TU_BIT(8)
2157#define PCGCCTL_DEEP_SLEEP TU_BIT(7)
2158#define PCGCCTL_PHY_IN_SLEEP TU_BIT(6)
2159#define PCGCCTL_ENBL_SLEEP_GATING TU_BIT(5)
2160#define PCGCCTL_RSTPDWNMODULE TU_BIT(3)
2161#define PCGCCTL_PWRCLMP TU_BIT(2)
2162#define PCGCCTL_GATEHCLK TU_BIT(1)
2163#define PCGCCTL_STOPPCLK TU_BIT(0)
2164
2165#define PCGCTL1_TIMER (0x3ul << 1)
2166#define PCGCTL1_GATEEN TU_BIT(0)
2167
2168#ifdef __cplusplus
2169 }
2170#endif
2171
2172#endif
dwc2_gotgctl_t
struct TU_ATTR_PACKED dwc2_gotgctl_t
dwc2_ghwcfg4_t
struct TU_ATTR_PACKED dwc2_ghwcfg4_t
dwc2_grxstsp_t
struct TU_ATTR_PACKED dwc2_grxstsp_t
dwc2_channel_tsize_t
struct TU_ATTR_PACKED dwc2_channel_tsize_t
GHWCFFG2_OPMODE_NON_OTG_DEVICE
@ GHWCFFG2_OPMODE_NON_OTG_DEVICE
Definition: dwc2_type.h:99
GHWCFG2_OPMODE_SRP
@ GHWCFG2_OPMODE_SRP
Definition: dwc2_type.h:96
GHWCFG2_OPMODE_SRP_HOST
@ GHWCFG2_OPMODE_SRP_HOST
Definition: dwc2_type.h:100
GHWCFG2_OPMODE_SRP_DEVICE
@ GHWCFG2_OPMODE_SRP_DEVICE
Definition: dwc2_type.h:98
GHWCFG2_OPMODE_HNP_SRP
@ GHWCFG2_OPMODE_HNP_SRP
Definition: dwc2_type.h:95
GHWCFG2_OPMODE_NON_OTG_HOST
@ GHWCFG2_OPMODE_NON_OTG_HOST
Definition: dwc2_type.h:101
GHWCFG2_OPMODE_NON_HNP_NON_SRP
@ GHWCFG2_OPMODE_NON_HNP_NON_SRP
Definition: dwc2_type.h:97
TU_VERIFY_STATIC
TU_VERIFY_STATIC(sizeof(dwc2_gotgctl_t)==4, "incorrect size")
dwc2_hptxsts_t
struct TU_ATTR_PACKED dwc2_hptxsts_t
HCTSIZ_PID_MDATA
@ HCTSIZ_PID_MDATA
Definition: dwc2_type.h:148
GHWCFG2_FSPHY_UTMI
@ GHWCFG2_FSPHY_UTMI
Definition: dwc2_type.h:120
GHWCFG2_FSPHY_NOT_SUPPORTED
@ GHWCFG2_FSPHY_NOT_SUPPORTED
Definition: dwc2_type.h:118
GHWCFG2_FSPHY_ULPI
@ GHWCFG2_FSPHY_ULPI
Definition: dwc2_type.h:121
GHWCFG2_FSPHY_DEDICATED
@ GHWCFG2_FSPHY_DEDICATED
Definition: dwc2_type.h:119
HCTSIZ_PID_DATA2
@ HCTSIZ_PID_DATA2
Definition: dwc2_type.h:143
HCTSIZ_PID_DATA1
@ HCTSIZ_PID_DATA1
Definition: dwc2_type.h:144
HCTSIZ_PID_DATA0
@ HCTSIZ_PID_DATA0
Definition: dwc2_type.h:142
HCTSIZ_PID_SETUP
@ HCTSIZ_PID_SETUP
Definition: dwc2_type.h:145
HPRT_SPEED_FULL
@ HPRT_SPEED_FULL
Definition: dwc2_type.h:132
HPRT_SPEED_HIGH
@ HPRT_SPEED_HIGH
Definition: dwc2_type.h:131
HPRT_SPEED_LOW
@ HPRT_SPEED_LOW
Definition: dwc2_type.h:133
GHWCFG2_HSPHY_UTMI
@ GHWCFG2_HSPHY_UTMI
Definition: dwc2_type.h:111
GHWCFG2_HSPHY_ULPI
@ GHWCFG2_HSPHY_ULPI
Definition: dwc2_type.h:112
GHWCFG2_HSPHY_NOT_SUPPORTED
@ GHWCFG2_HSPHY_NOT_SUPPORTED
Definition: dwc2_type.h:110
GHWCFG2_HSPHY_UTMI_ULPI
@ GHWCFG2_HSPHY_UTMI_ULPI
Definition: dwc2_type.h:113
HCCHAR_EPTYPE_CONTROL
@ HCCHAR_EPTYPE_CONTROL
Definition: dwc2_type.h:168
HCCHAR_EPTYPE_BULK
@ HCCHAR_EPTYPE_BULK
Definition: dwc2_type.h:170
HCCHAR_EPTYPE_INTERRUPT
@ HCCHAR_EPTYPE_INTERRUPT
Definition: dwc2_type.h:171
HCCHAR_EPTYPE_ISOCHRONOUS
@ HCCHAR_EPTYPE_ISOCHRONOUS
Definition: dwc2_type.h:169
dwc2_gotgint_t
struct TU_ATTR_PACKED dwc2_gotgint_t
dwc2_ep_tsize_t
struct TU_ATTR_PACKED dwc2_ep_tsize_t
GINTSTS_CMODE_HOST
@ GINTSTS_CMODE_HOST
Definition: dwc2_type.h:138
GINTSTS_CMODE_DEVICE
@ GINTSTS_CMODE_DEVICE
Definition: dwc2_type.h:137
dwc2_grstctl_t
struct TU_ATTR_PACKED dwc2_grstctl_t
GRXSTS_PKTSTS_GLOBALOUTNAK
@ GRXSTS_PKTSTS_GLOBALOUTNAK
Definition: dwc2_type.h:152
GRXSTS_PKTSTS_SETUPDONE
@ GRXSTS_PKTSTS_SETUPDONE
Definition: dwc2_type.h:155
GRXSTS_PKTSTS_SETUPRX
@ GRXSTS_PKTSTS_SETUPRX
Definition: dwc2_type.h:156
GRXSTS_PKTSTS_OUTDONE
@ GRXSTS_PKTSTS_OUTDONE
Definition: dwc2_type.h:154
GRXSTS_PKTSTS_OUTRX
@ GRXSTS_PKTSTS_OUTRX
Definition: dwc2_type.h:153
GHWCFFG4_PHY_DATA_WIDTH_8_16
@ GHWCFFG4_PHY_DATA_WIDTH_8_16
Definition: dwc2_type.h:127
GHWCFFG4_PHY_DATA_WIDTH_16
@ GHWCFFG4_PHY_DATA_WIDTH_16
Definition: dwc2_type.h:126
GHWCFFG4_PHY_DATA_WIDTH_8
@ GHWCFFG4_PHY_DATA_WIDTH_8
Definition: dwc2_type.h:125
dwc2_gahbcfg_t
struct TU_ATTR_PACKED dwc2_gahbcfg_t
dwc2_channel_char_t
struct TU_ATTR_PACKED dwc2_channel_char_t
dwc2_gusbcfg_t
struct TU_ATTR_PACKED dwc2_gusbcfg_t
dwc2_channel_split_t
struct TU_ATTR_PACKED dwc2_channel_split_t
GOTGCTL_OTG_VERSION_1_3
@ GOTGCTL_OTG_VERSION_1_3
Definition: dwc2_type.h:90
GOTGCTL_OTG_VERSION_2_0
@ GOTGCTL_OTG_VERSION_2_0
Definition: dwc2_type.h:91
GRXSTS_PKTSTS_HOST_CHANNEL_HALTED
@ GRXSTS_PKTSTS_HOST_CHANNEL_HALTED
Definition: dwc2_type.h:163
GRXSTS_PKTSTS_RX_COMPLETE
@ GRXSTS_PKTSTS_RX_COMPLETE
Definition: dwc2_type.h:161
GRXSTS_PKTSTS_RX_DATA
@ GRXSTS_PKTSTS_RX_DATA
Definition: dwc2_type.h:160
GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR
@ GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR
Definition: dwc2_type.h:162
dwc2_ghwcfg2_t
struct TU_ATTR_PACKED dwc2_ghwcfg2_t
GHWCFG2_ARCH_EXTERNAL_DMA
@ GHWCFG2_ARCH_EXTERNAL_DMA
Definition: dwc2_type.h:105
GHWCFG2_ARCH_SLAVE_ONLY
@ GHWCFG2_ARCH_SLAVE_ONLY
Definition: dwc2_type.h:104
GHWCFG2_ARCH_INTERNAL_DMA
@ GHWCFG2_ARCH_INTERNAL_DMA
Definition: dwc2_type.h:106
dwc2_hnptxsts_t
struct TU_ATTR_PACKED dwc2_hnptxsts_t
dwc2_ghwcfg3_t
struct TU_ATTR_PACKED dwc2_ghwcfg3_t
dwc2_hfnum_t
struct TU_ATTR_PACKED dwc2_hfnum_t
dwc2_hprt_t
struct TU_ATTR_PACKED dwc2_hprt_t
HS_PHYC_GlobalTypeDef
Definition: dwc2_type.h:78
HS_PHYC_GlobalTypeDef::HS_PHYC_LDO
volatile uint32_t HS_PHYC_LDO
Definition: dwc2_type.h:85
HS_PHYC_GlobalTypeDef::HS_PHYC_PLL
volatile uint32_t HS_PHYC_PLL
Definition: dwc2_type.h:79
HS_PHYC_GlobalTypeDef::Reserved10
volatile uint32_t Reserved10
Definition: dwc2_type.h:83
HS_PHYC_GlobalTypeDef::HS_PHYC_TUNE
volatile uint32_t HS_PHYC_TUNE
Definition: dwc2_type.h:82
HS_PHYC_GlobalTypeDef::Reserved04
volatile uint32_t Reserved04
Definition: dwc2_type.h:80
HS_PHYC_GlobalTypeDef::Reserved14
volatile uint32_t Reserved14
Definition: dwc2_type.h:84
HS_PHYC_GlobalTypeDef::Reserved08
volatile uint32_t Reserved08
Definition: dwc2_type.h:81
TU_ATTR_PACKED
AUDIO Channel Cluster Descriptor (4.1)
Definition: audio.h:647
TU_ATTR_PACKED::ses_req_scs
uint32_t ses_req_scs
Definition: dwc2_type.h:178
TU_ATTR_PACKED::pid
uint32_t pid
Definition: dwc2_type.h:436
TU_ATTR_PACKED::num_host_ch
uint32_t num_host_ch
Definition: dwc2_type.h:310
TU_ATTR_PACKED::phy_data_width
uint32_t phy_data_width
Definition: dwc2_type.h:350
TU_ATTR_PACKED::power
uint32_t power
Definition: dwc2_type.h:401
TU_ATTR_PACKED::ep_type
uint32_t ep_type
Definition: dwc2_type.h:414
TU_ATTR_PACKED::fs_phy_type
uint32_t fs_phy_type
Definition: dwc2_type.h:308
TU_ATTR_PACKED::intoken_q_flush
uint32_t intoken_q_flush
Definition: dwc2_type.h:281
TU_ATTR_PACKED::rsv13_14
uint32_t rsv13_14
Definition: dwc2_type.h:191
TU_ATTR_PACKED::vendor_ctrl_itf
uint32_t vendor_ctrl_itf
Definition: dwc2_type.h:327
TU_ATTR_PACKED::nptxf_empty_lvl
uint32_t nptxf_empty_lvl
Definition: dwc2_type.h:226
TU_ATTR_PACKED::rsv19_31
uint32_t rsv19_31
Definition: dwc2_type.h:404
TU_ATTR_PACKED::dma_req
uint32_t dma_req
Definition: dwc2_type.h:287
TU_ATTR_PACKED::chirp_en
uint32_t chirp_en
Definition: dwc2_type.h:200
TU_ATTR_PACKED::line_status
uint32_t line_status
Definition: dwc2_type.h:400
TU_ATTR_PACKED::mul_proc_intrpt
uint32_t mul_proc_intrpt
Definition: dwc2_type.h:313
TU_ATTR_PACKED::bses_valid
uint32_t bses_valid
Definition: dwc2_type.h:196
TU_ATTR_PACKED::a_valid_filter
uint32_t a_valid_filter
Definition: dwc2_type.h:354
TU_ATTR_PACKED::rsv16
uint32_t rsv16
Definition: dwc2_type.h:412
TU_ATTR_PACKED::ep_num
uint32_t ep_num
Definition: dwc2_type.h:410
TU_ATTR_PACKED::rx_fifo_flush
uint32_t rx_fifo_flush
Definition: dwc2_type.h:282
TU_ATTR_PACKED::rsv3_7
uint32_t rsv3_7
Definition: dwc2_type.h:209
TU_ATTR_PACKED::split_en
uint32_t split_en
Definition: dwc2_type.h:429
TU_ATTR_PACKED::iddg_filter
uint32_t iddg_filter
Definition: dwc2_type.h:352
TU_ATTR_PACKED::b_valid_filter
uint32_t b_valid_filter
Definition: dwc2_type.h:355
TU_ATTR_PACKED::qtop_ch_num
uint32_t qtop_ch_num
Definition: dwc2_type.h:374
TU_ATTR_PACKED::remote_mem_support
uint32_t remote_mem_support
Definition: dwc2_type.h:229
TU_ATTR_PACKED::phy_low_power_clk_sel
uint32_t phy_low_power_clk_sel
Definition: dwc2_type.h:253
TU_ATTR_PACKED::over_current_active
uint32_t over_current_active
Definition: dwc2_type.h:394
TU_ATTR_PACKED::tx_end_delay
uint32_t tx_end_delay
Definition: dwc2_type.h:270
TU_ATTR_PACKED::rsv21_31
uint32_t rsv21_31
Definition: dwc2_type.h:217
TU_ATTR_PACKED::dpid
uint32_t dpid
Definition: dwc2_type.h:295
TU_ATTR_PACKED::packet_size_width
uint32_t packet_size_width
Definition: dwc2_type.h:324
TU_ATTR_PACKED::indicator_pass_through
uint32_t indicator_pass_through
Definition: dwc2_type.h:266
TU_ATTR_PACKED::packet_count
uint32_t packet_count
Definition: dwc2_type.h:435
TU_ATTR_PACKED::rsv9
uint32_t rsv9
Definition: dwc2_type.h:399
TU_ATTR_PACKED::num_dev_ep
uint32_t num_dev_ep
Definition: dwc2_type.h:309
TU_ATTR_PACKED::dma_desc_dynamic
uint32_t dma_desc_dynamic
Definition: dwc2_type.h:360
TU_ATTR_PACKED::rsv11_28
uint32_t rsv11_28
Definition: dwc2_type.h:285
TU_ATTR_PACKED::ulpi_auto_resume
uint32_t ulpi_auto_resume
Definition: dwc2_type.h:260
TU_ATTR_PACKED::num
uint32_t num
Definition: dwc2_type.h:442
TU_ATTR_PACKED::hub_addr
uint32_t hub_addr
Definition: dwc2_type.h:425
TU_ATTR_PACKED::test_mode_corr_eusb2
uint32_t test_mode_corr_eusb2
Definition: dwc2_type.h:202
TU_ATTR_PACKED::dfifo_depth
uint32_t dfifo_depth
Definition: dwc2_type.h:334
TU_ATTR_PACKED::vbval_ov_val
uint32_t vbval_ov_val
Definition: dwc2_type.h:181
TU_ATTR_PACKED::core_soft_rst
uint32_t core_soft_rst
Definition: dwc2_type.h:278
TU_ATTR_PACKED::ipg_isoc_support
uint32_t ipg_isoc_support
Definition: dwc2_type.h:347
TU_ATTR_PACKED::hnp_rq
uint32_t hnp_rq
Definition: dwc2_type.h:187
TU_ATTR_PACKED::extended_hibernation
uint32_t extended_hibernation
Definition: dwc2_type.h:343
TU_ATTR_PACKED::ahb_freq_min
uint32_t ahb_freq_min
Definition: dwc2_type.h:341
TU_ATTR_PACKED::i2c_enable
uint32_t i2c_enable
Definition: dwc2_type.h:326
TU_ATTR_PACKED::byte_count
uint32_t byte_count
Definition: dwc2_type.h:294
TU_ATTR_PACKED::conn_detected
uint32_t conn_detected
Definition: dwc2_type.h:391
TU_ATTR_PACKED::ases_valid
uint32_t ases_valid
Definition: dwc2_type.h:195
TU_ATTR_PACKED::otg_adp_support
uint32_t otg_adp_support
Definition: dwc2_type.h:330
TU_ATTR_PACKED::qtop_odd_frame
uint32_t qtop_odd_frame
Definition: dwc2_type.h:385
TU_ATTR_PACKED::err_multi_count
uint32_t err_multi_count
Definition: dwc2_type.h:415
TU_ATTR_PACKED::reset
uint32_t reset
Definition: dwc2_type.h:398
TU_ATTR_PACKED::nptx_q_depth
uint32_t nptx_q_depth
Definition: dwc2_type.h:315
TU_ATTR_PACKED::session_end_filter
uint32_t session_end_filter
Definition: dwc2_type.h:356
TU_ATTR_PACKED::rsv28_30
uint32_t rsv28_30
Definition: dwc2_type.h:201
TU_ATTR_PACKED::req_queue_available
uint32_t req_queue_available
Definition: dwc2_type.h:370
TU_ATTR_PACKED::gintmask
uint32_t gintmask
Definition: dwc2_type.h:222
TU_ATTR_PACKED::token_q_depth
uint32_t token_q_depth
Definition: dwc2_type.h:317
TU_ATTR_PACKED::single_point
uint32_t single_point
Definition: dwc2_type.h:306
TU_ATTR_PACKED::ddr_sel
uint32_t ddr_sel
Definition: dwc2_type.h:248
TU_ATTR_PACKED::current_mode
uint32_t current_mode
Definition: dwc2_type.h:198
TU_ATTR_PACKED::ses_end_det
uint32_t ses_end_det
Definition: dwc2_type.h:208
TU_ATTR_PACKED::tx_fifo_flush
uint32_t tx_fifo_flush
Definition: dwc2_type.h:283
TU_ATTR_PACKED::num_dev_period_in_ep
uint32_t num_dev_period_in_ep
Definition: dwc2_type.h:339
TU_ATTR_PACKED::enable_change
uint32_t enable_change
Definition: dwc2_type.h:393
TU_ATTR_PACKED::ic_usb_capable
uint32_t ic_usb_capable
Definition: dwc2_type.h:268
TU_ATTR_PACKED::dedicated_fifos
uint32_t dedicated_fifos
Definition: dwc2_type.h:357
TU_ATTR_PACKED::dbnc_filter_bypass
uint32_t dbnc_filter_bypass
Definition: dwc2_type.h:192
TU_ATTR_PACKED::ic_usb_traf_ctl
uint32_t ic_usb_traf_ctl
Definition: dwc2_type.h:269
TU_ATTR_PACKED::packet_status
uint32_t packet_status
Definition: dwc2_type.h:296
TU_ATTR_PACKED::hns_status_change
uint32_t hns_status_change
Definition: dwc2_type.h:211
TU_ATTR_PACKED::cid_status
uint32_t cid_status
Definition: dwc2_type.h:193
TU_ATTR_PACKED::term_sel_dl_pulse
uint32_t term_sel_dl_pulse
Definition: dwc2_type.h:264
TU_ATTR_PACKED::timeout_cal
uint32_t timeout_cal
Definition: dwc2_type.h:238
TU_ATTR_PACKED::srp_capable
uint32_t srp_capable
Definition: dwc2_type.h:249
TU_ATTR_PACKED::frame_number
uint32_t frame_number
Definition: dwc2_type.h:297
TU_ATTR_PACKED::enhanced_lpm_support1
uint32_t enhanced_lpm_support1
Definition: dwc2_type.h:345
TU_ATTR_PACKED::ulpi_ext_vbus_drv
uint32_t ulpi_ext_vbus_drv
Definition: dwc2_type.h:262
TU_ATTR_PACKED::core_soft_rst_done
uint32_t core_soft_rst_done
Definition: dwc2_type.h:286
TU_ATTR_PACKED::dma_en
uint32_t dma_en
Definition: dwc2_type.h:224
TU_ATTR_PACKED::xfer_size_width
uint32_t xfer_size_width
Definition: dwc2_type.h:323
TU_ATTR_PACKED::tx_fifo_num
uint32_t tx_fifo_num
Definition: dwc2_type.h:284
TU_ATTR_PACKED::phy_if16
uint32_t phy_if16
Definition: dwc2_type.h:244
TU_ATTR_PACKED::ptxf_empty_lvl
uint32_t ptxf_empty_lvl
Definition: dwc2_type.h:227
TU_ATTR_PACKED::dbnc_done
uint32_t dbnc_done
Definition: dwc2_type.h:194
TU_ATTR_PACKED::srs_status_change
uint32_t srs_status_change
Definition: dwc2_type.h:210
TU_ATTR_PACKED::lpm_mode
uint32_t lpm_mode
Definition: dwc2_type.h:333
TU_ATTR_PACKED::xfer_size
uint32_t xfer_size
Definition: dwc2_type.h:434
TU_ATTR_PACKED::acg_support
uint32_t acg_support
Definition: dwc2_type.h:348
TU_ATTR_PACKED::ahb_idle
uint32_t ahb_idle
Definition: dwc2_type.h:288
TU_ATTR_PACKED::ulpi_int_vbus_indicator
uint32_t ulpi_int_vbus_indicator
Definition: dwc2_type.h:263
TU_ATTR_PACKED::mult_val_id_bc
uint32_t mult_val_id_bc
Definition: dwc2_type.h:199
TU_ATTR_PACKED::rsv14
uint32_t rsv14
Definition: dwc2_type.h:252
TU_ATTR_PACKED::remainning
uint32_t remainning
Definition: dwc2_type.h:443
TU_ATTR_PACKED::reserved8
uint32_t reserved8
Definition: dwc2_type.h:344
TU_ATTR_PACKED::rsv25_31
uint32_t rsv25_31
Definition: dwc2_type.h:233
TU_ATTR_PACKED::rsv6
uint32_t rsv6
Definition: dwc2_type.h:225
TU_ATTR_PACKED::mc_pid
uint32_t mc_pid
Definition: dwc2_type.h:474
TU_ATTR_PACKED::rsv9_20
uint32_t rsv9_20
Definition: dwc2_type.h:228
TU_ATTR_PACKED::hng_scs
uint32_t hng_scs
Definition: dwc2_type.h:186
TU_ATTR_PACKED::indicator_complement
uint32_t indicator_complement
Definition: dwc2_type.h:265
TU_ATTR_PACKED::bval_ov_en
uint32_t bval_ov_en
Definition: dwc2_type.h:184
TU_ATTR_PACKED::test_control
uint32_t test_control
Definition: dwc2_type.h:402
TU_ATTR_PACKED::arch
uint32_t arch
Definition: dwc2_type.h:305
TU_ATTR_PACKED::battery_charger_support
uint32_t battery_charger_support
Definition: dwc2_type.h:332
TU_ATTR_PACKED::otg_enable_ic_usb
uint32_t otg_enable_ic_usb
Definition: dwc2_type.h:318
TU_ATTR_PACKED::over_current_change
uint32_t over_current_change
Definition: dwc2_type.h:395
TU_ATTR_PACKED::op_mode
uint32_t op_mode
Definition: dwc2_type.h:304
TU_ATTR_PACKED::fifo_available
uint32_t fifo_available
Definition: dwc2_type.h:369
TU_ATTR_PACKED::conn_status
uint32_t conn_status
Definition: dwc2_type.h:390
TU_ATTR_PACKED::hnp_capable
uint32_t hnp_capable
Definition: dwc2_type.h:250
TU_ATTR_PACKED::hng_det
uint32_t hng_det
Definition: dwc2_type.h:213
TU_ATTR_PACKED::embedded_host_en
uint32_t embedded_host_en
Definition: dwc2_type.h:190
TU_ATTR_PACKED::ep_ch_num
uint32_t ep_ch_num
Definition: dwc2_type.h:293
TU_ATTR_PACKED::optional_feature_removed
uint32_t optional_feature_removed
Definition: dwc2_type.h:328
TU_ATTR_PACKED::speed
uint32_t speed
Definition: dwc2_type.h:403
TU_ATTR_PACKED::phy_sel
uint32_t phy_sel
Definition: dwc2_type.h:247
TU_ATTR_PACKED::vbus_valid_filter
uint32_t vbus_valid_filter
Definition: dwc2_type.h:353
TU_ATTR_PACKED::notify_all_dma_write
uint32_t notify_all_dma_write
Definition: dwc2_type.h:230
TU_ATTR_PACKED::rsv10_16
uint32_t rsv10_16
Definition: dwc2_type.h:212
TU_ATTR_PACKED::piufs_soft_rst
uint32_t piufs_soft_rst
Definition: dwc2_type.h:279
TU_ATTR_PACKED::low_speed_dev
uint32_t low_speed_dev
Definition: dwc2_type.h:413
TU_ATTR_PACKED::hub_port
uint32_t hub_port
Definition: dwc2_type.h:424
TU_ATTR_PACKED::enable_dynamic_fifo
uint32_t enable_dynamic_fifo
Definition: dwc2_type.h:312
TU_ATTR_PACKED::otg_i2c_sel
uint32_t otg_i2c_sel
Definition: dwc2_type.h:257
TU_ATTR_PACKED::dma_desc_enabled
uint32_t dma_desc_enabled
Definition: dwc2_type.h:359
TU_ATTR_PACKED::ptx_q_depth
uint32_t ptx_q_depth
Definition: dwc2_type.h:316
TU_ATTR_PACKED::qtop_last_period
uint32_t qtop_last_period
Definition: dwc2_type.h:382
TU_ATTR_PACKED::dev_hnp_en
uint32_t dev_hnp_en
Definition: dwc2_type.h:189
TU_ATTR_PACKED::qtop_type
uint32_t qtop_type
Definition: dwc2_type.h:373
TU_ATTR_PACKED::odd_frame
uint32_t odd_frame
Definition: dwc2_type.h:417
TU_ATTR_PACKED::force_host_mode
uint32_t force_host_mode
Definition: dwc2_type.h:271
TU_ATTR_PACKED::inv_desc_endian
uint32_t inv_desc_endian
Definition: dwc2_type.h:232
TU_ATTR_PACKED::enable
uint32_t enable
Definition: dwc2_type.h:392
TU_ATTR_PACKED::adev_timeout_change
uint32_t adev_timeout_change
Definition: dwc2_type.h:214
TU_ATTR_PACKED::rsv17_30
uint32_t rsv17_30
Definition: dwc2_type.h:428
TU_ATTR_PACKED::aval_ov_en
uint32_t aval_ov_en
Definition: dwc2_type.h:182
TU_ATTR_PACKED::xact_pos
uint32_t xact_pos
Definition: dwc2_type.h:426
TU_ATTR_PACKED::resume
uint32_t resume
Definition: dwc2_type.h:396
TU_ATTR_PACKED::ses_req
uint32_t ses_req
Definition: dwc2_type.h:179
TU_ATTR_PACKED::ep_dir
uint32_t ep_dir
Definition: dwc2_type.h:411
TU_ATTR_PACKED::ulpi_utmi_sel
uint32_t ulpi_utmi_sel
Definition: dwc2_type.h:245
TU_ATTR_PACKED::period_channel_support
uint32_t period_channel_support
Definition: dwc2_type.h:311
TU_ATTR_PACKED::partial_powerdown
uint32_t partial_powerdown
Definition: dwc2_type.h:340
TU_ATTR_PACKED::rsv0_1
uint32_t rsv0_1
Definition: dwc2_type.h:207
TU_ATTR_PACKED::synch_reset
uint32_t synch_reset
Definition: dwc2_type.h:329
TU_ATTR_PACKED::reserved21
uint32_t reserved21
Definition: dwc2_type.h:314
TU_ATTR_PACKED::turnaround_time
uint32_t turnaround_time
Definition: dwc2_type.h:251
TU_ATTR_PACKED::ahb_single
uint32_t ahb_single
Definition: dwc2_type.h:231
TU_ATTR_PACKED::service_interval_flow
uint32_t service_interval_flow
Definition: dwc2_type.h:346
TU_ATTR_PACKED::dev_addr
uint32_t dev_addr
Definition: dwc2_type.h:416
TU_ATTR_PACKED::hbst_len
uint32_t hbst_len
Definition: dwc2_type.h:223
TU_ATTR_PACKED::corrupt_tx_pkt
uint32_t corrupt_tx_pkt
Definition: dwc2_type.h:273
TU_ATTR_PACKED::ep_size
uint32_t ep_size
Definition: dwc2_type.h:409
TU_ATTR_PACKED::otg_ver
uint32_t otg_ver
Definition: dwc2_type.h:197
TU_ATTR_PACKED::disable
uint32_t disable
Definition: dcd_lpc_ip3511.c:156
TU_ATTR_PACKED::fs_intf_sel
uint32_t fs_intf_sel
Definition: dwc2_type.h:246
TU_ATTR_PACKED::otg_enable_hsic
uint32_t otg_enable_hsic
Definition: dwc2_type.h:331
TU_ATTR_PACKED::enhanced_lpm_support
uint32_t enhanced_lpm_support
Definition: dwc2_type.h:349
TU_ATTR_PACKED::force_dev_mode
uint32_t force_dev_mode
Definition: dwc2_type.h:272
TU_ATTR_PACKED::mult_val_lp_change
uint32_t mult_val_lp_change
Definition: dwc2_type.h:216
TU_ATTR_PACKED::qtop_terminate
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Definition: dwc2_type.h:372
TU_ATTR_PACKED::host_set_hnp_en
uint32_t host_set_hnp_en
Definition: dwc2_type.h:188
TU_ATTR_PACKED::ulpi_clk_sus_m
uint32_t ulpi_clk_sus_m
Definition: dwc2_type.h:261
TU_ATTR_PACKED::split_compl
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Definition: dwc2_type.h:427
TU_ATTR_PACKED::ulpi_if_protect_disable
uint32_t ulpi_if_protect_disable
Definition: dwc2_type.h:267
TU_ATTR_PACKED::hibernation
uint32_t hibernation
Definition: dwc2_type.h:342
TU_ATTR_PACKED::hs_phy_type
uint32_t hs_phy_type
Definition: dwc2_type.h:307
TU_ATTR_PACKED::num_dev_in_eps
uint32_t num_dev_in_eps
Definition: dwc2_type.h:358
TU_ATTR_PACKED::frame_counter_rst
uint32_t frame_counter_rst
Definition: dwc2_type.h:280
TU_ATTR_PACKED::aval_ov_al
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Definition: dwc2_type.h:183
TU_ATTR_PACKED::otg_enable
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Definition: dwc2_type.h:325
TU_ATTR_PACKED::ctrl_ep_num
uint32_t ctrl_ep_num
Definition: dwc2_type.h:351
TU_ATTR_PACKED::ulpi_fsls
uint32_t ulpi_fsls
Definition: dwc2_type.h:258
TU_ATTR_PACKED::bval_ov_val
uint32_t bval_ov_val
Definition: dwc2_type.h:185
TU_ATTR_PACKED::do_ping
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Definition: dwc2_type.h:437
TU_ATTR_PACKED::suspend
uint32_t suspend
Definition: dwc2_type.h:397
TU_ATTR_PACKED::vbval_ov_en
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Definition: dwc2_type.h:180
dwc2_channel_t
Definition: dwc2_type.h:448
dwc2_channel_t::hctsiz_bm
volatile dwc2_channel_tsize_t hctsiz_bm
Definition: dwc2_type.h:461
dwc2_channel_t::hcint
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Definition: dwc2_type.h:457
dwc2_channel_t::hcsplt
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Definition: dwc2_type.h:454
dwc2_channel_t::reserved518
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Definition: dwc2_type.h:464
dwc2_channel_t::hcdmab
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Definition: dwc2_type.h:465
dwc2_channel_t::hcchar_bm
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Definition: dwc2_type.h:451
dwc2_channel_t::hctsiz
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Definition: dwc2_type.h:460
dwc2_channel_t::hcintmsk
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Definition: dwc2_type.h:458
dwc2_channel_t::hcsplt_bm
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Definition: dwc2_type.h:455
dwc2_channel_t::hcdma
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Definition: dwc2_type.h:463
dwc2_channel_t::hcchar
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Definition: dwc2_type.h:450
dwc2_dep_t
Definition: dwc2_type.h:508
dwc2_dep_t::rsv0c
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Definition: dwc2_type.h:519
dwc2_dep_t::doeptsiz
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Definition: dwc2_type.h:522
dwc2_dep_t::rsv04
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Definition: dwc2_type.h:514
dwc2_dep_t::dieptsiz
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Definition: dwc2_type.h:521
dwc2_dep_t::diepctl
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Definition: dwc2_type.h:510
dwc2_dep_t::doepint
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Definition: dwc2_type.h:517
dwc2_dep_t::diepdma
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Definition: dwc2_type.h:526
dwc2_dep_t::dtxfsts
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Definition: dwc2_type.h:529
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Definition: dwc2_type.h:527
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Definition: dwc2_type.h:511
dwc2_dep_t::diepint
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Definition: dwc2_type.h:516
dwc2_dep_t::rsv1c
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Definition: dwc2_type.h:530
dwc2_dep_t::ctl
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Definition: dwc2_type.h:512
dwc2_dep_t::deptsiz_bm
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Definition: dwc2_type.h:523
dwc2_epin_t
Definition: dwc2_type.h:479
dwc2_epin_t::dieptsiz_bm
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Definition: dwc2_type.h:486
dwc2_epin_t::dtxfsts
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Definition: dwc2_type.h:489
dwc2_epin_t::dieptsiz
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Definition: dwc2_type.h:485
dwc2_epin_t::reserved1c
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Definition: dwc2_type.h:490
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Definition: dwc2_type.h:481
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Definition: dwc2_type.h:480
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Definition: dwc2_type.h:488
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Definition: dwc2_type.h:483
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Definition: dwc2_type.h:482
dwc2_epout_t
Definition: dwc2_type.h:494
dwc2_epout_t::doeptsiz
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Definition: dwc2_type.h:500
dwc2_epout_t::doepctl
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Definition: dwc2_type.h:495
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Definition: dwc2_type.h:501
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Definition: dwc2_type.h:497
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Definition: dwc2_type.h:496
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Definition: dwc2_type.h:503
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Definition: dwc2_type.h:498
dwc2_regs_t
Definition: dwc2_type.h:538
dwc2_regs_t::hfnum_bm
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Definition: dwc2_type.h:612
dwc2_regs_t::gahbcfg
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Definition: dwc2_type.h:549
dwc2_regs_t::hcfg
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Definition: dwc2_type.h:608
dwc2_regs_t::gnptxfsiz
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Definition: dwc2_type.h:570
dwc2_regs_t::hptxsts_bm
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Definition: dwc2_type.h:617
dwc2_regs_t::gadpctl
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Definition: dwc2_type.h:601
dwc2_regs_t::gotgctl_bm
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Definition: dwc2_type.h:542
dwc2_regs_t::diepempmsk
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Definition: dwc2_type.h:647
dwc2_regs_t::hflbaddr
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Definition: dwc2_type.h:621
dwc2_regs_t::daintmsk
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Definition: dwc2_type.h:641
dwc2_regs_t::gotgctl
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Definition: dwc2_type.h:541
dwc2_regs_t::ggpio
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Definition: dwc2_type.h:580
dwc2_regs_t::daint
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Definition: dwc2_type.h:640
dwc2_regs_t::ghwcfg2
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Definition: dwc2_type.h:587
dwc2_regs_t::hfir
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Definition: dwc2_type.h:609
dwc2_regs_t::gotgint
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Definition: dwc2_type.h:545
dwc2_regs_t::grxfsiz
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Definition: dwc2_type.h:567
dwc2_regs_t::stm32_gccfg
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Definition: dwc2_type.h:581
dwc2_regs_t::gusbcfg
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Definition: dwc2_type.h:553
dwc2_regs_t::hptxfsiz
volatile uint32_t hptxfsiz
Definition: dwc2_type.h:603
dwc2_regs_t::hprt_bm
volatile dwc2_hprt_t hprt_bm
Definition: dwc2_type.h:625
dwc2_regs_t::gsnpsid
volatile uint32_t gsnpsid
Definition: dwc2_type.h:584
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volatile uint32_t dieptxf0
Definition: dwc2_type.h:569
dwc2_regs_t::grstctl_bm
volatile dwc2_grstctl_t grstctl_bm
Definition: dwc2_type.h:558
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volatile uint32_t dvbusdis
Definition: dwc2_type.h:644
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Definition: dwc2_type.h:611
dwc2_regs_t::haintmsk
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Definition: dwc2_type.h:620
dwc2_regs_t::deachint
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Definition: dwc2_type.h:651
dwc2_regs_t::grxstsp_bm
volatile dwc2_grxstsp_t grxstsp_bm
Definition: dwc2_type.h:565
dwc2_regs_t::hprt
volatile uint32_t hprt
Definition: dwc2_type.h:624
dwc2_regs_t::diepmsk
volatile uint32_t diepmsk
Definition: dwc2_type.h:638
dwc2_regs_t::ghwcfg2_bm
volatile dwc2_ghwcfg2_t ghwcfg2_bm
Definition: dwc2_type.h:588
dwc2_regs_t::ghwcfg4
volatile uint32_t ghwcfg4
Definition: dwc2_type.h:595
dwc2_regs_t::gpwrdn
volatile uint32_t gpwrdn
Definition: dwc2_type.h:599
dwc2_regs_t::ghwcfg4_bm
volatile dwc2_ghwcfg4_t ghwcfg4_bm
Definition: dwc2_type.h:596
dwc2_regs_t::gahbcfg_bm
volatile dwc2_gahbcfg_t gahbcfg_bm
Definition: dwc2_type.h:550
dwc2_regs_t::dtknqr1
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Definition: dwc2_type.h:642
dwc2_regs_t::hptxsts
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Definition: dwc2_type.h:616
dwc2_regs_t::hnptxsts
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Definition: dwc2_type.h:573
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Definition: dwc2_type.h:546
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Definition: dwc2_type.h:636
dwc2_regs_t::grxstsp
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Definition: dwc2_type.h:564
dwc2_regs_t::deachmsk
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Definition: dwc2_type.h:652
dwc2_regs_t::dthrctl
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Definition: dwc2_type.h:646
dwc2_regs_t::glpmcfg
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Definition: dwc2_type.h:598
dwc2_regs_t::gpvndctl
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Definition: dwc2_type.h:578
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Definition: dwc2_type.h:574
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volatile dwc2_gusbcfg_t gusbcfg_bm
Definition: dwc2_type.h:554
dwc2_regs_t::gintmsk
volatile uint32_t gintmsk
Definition: dwc2_type.h:561
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Definition: dwc2_type.h:639
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Definition: dwc2_type.h:614
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Definition: dwc2_type.h:575
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Definition: dwc2_type.h:669
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Definition: dwc2_type.h:557
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Definition: dwc2_type.h:560
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Definition: dwc2_type.h:643
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Definition: dwc2_type.h:634
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Definition: dwc2_type.h:637
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Definition: dwc2_type.h:577
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Definition: dwc2_type.h:583
dwc2_regs_t::ghwcfg1
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Definition: dwc2_type.h:585
dwc2_regs_t::pcgcctl
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Definition: dwc2_type.h:668
dwc2_regs_t::ghwcfg3_bm
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Definition: dwc2_type.h:592
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Definition: dwc2_type.h:635
dwc2_regs_t::ghwcfg3
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Definition: dwc2_type.h:591
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Definition: dwc2_type.h:600
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Definition: dwc2_type.h:619
dwc2_regs_t::dvbuspulse
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Definition: dwc2_type.h:645
dwc2_regs_t::grxstsr
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Definition: dwc2_type.h:562