Open FFBoard
Open source force feedback firmware
dcd_samd.c
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1/*
2 * The MIT License (MIT)
3 *
4 * Copyright (c) 2018 Scott Shawcroft for Adafruit Industries
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 *
24 * This file is part of the TinyUSB stack.
25 */
26
27#include "tusb_option.h"
28
29#if CFG_TUD_ENABLED && \
30 (CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
31 CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
32 CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21)
33
34#include "sam.h"
35#include "device/dcd.h"
36
37/*------------------------------------------------------------------*/
38/* MACRO TYPEDEF CONSTANT ENUM
39 *------------------------------------------------------------------*/
40static TU_ATTR_ALIGNED(4) UsbDeviceDescBank sram_registers[8][2];
41
42// Setup packet is only 8 bytes in length. However under certain scenario,
43// USB DMA controller may decide to overwrite/overflow the buffer with
44// 2 extra bytes of CRC. From datasheet's "Management of SETUP Transactions" section
45// If the number of received data bytes is the maximum data payload specified by
46// PCKSIZE.SIZE minus one, only the first CRC data is written to the data buffer.
47// If the number of received data is equal or less than the data payload specified
48// by PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
49// Therefore we will need to increase it to 10 bytes here.
50static TU_ATTR_ALIGNED(4) uint8_t _setup_packet[8+2];
51
52// ready for receiving SETUP packet
53static inline void prepare_setup(void)
54{
55 // Only make sure the EP0 OUT buffer is ready
56 sram_registers[0][0].ADDR.reg = (uint32_t) _setup_packet;
57 sram_registers[0][0].PCKSIZE.bit.MULTI_PACKET_SIZE = sizeof(tusb_control_request_t);
58 sram_registers[0][0].PCKSIZE.bit.BYTE_COUNT = 0;
59}
60
61// Setup the control endpoint 0.
62static void bus_reset(void)
63{
64 // Max size of packets is 64 bytes.
65 UsbDeviceDescBank* bank_out = &sram_registers[0][TUSB_DIR_OUT];
66 bank_out->PCKSIZE.bit.SIZE = 0x3;
67 UsbDeviceDescBank* bank_in = &sram_registers[0][TUSB_DIR_IN];
68 bank_in->PCKSIZE.bit.SIZE = 0x3;
69
70 UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[0];
71 ep->EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0x1) | USB_DEVICE_EPCFG_EPTYPE1(0x1);
72 ep->EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1 | USB_DEVICE_EPINTENSET_RXSTP;
73
74 // Prepare for setup packet
75 prepare_setup();
76}
77
78/*------------------------------------------------------------------*/
79/* Controller API
80 *------------------------------------------------------------------*/
81bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
82 (void) rhport;
83 (void) rh_init;
84
85 // Reset to get in a clean state.
86 USB->DEVICE.CTRLA.bit.SWRST = true;
87 while (USB->DEVICE.SYNCBUSY.bit.SWRST == 0) {}
88 while (USB->DEVICE.SYNCBUSY.bit.SWRST == 1) {}
89
90 USB->DEVICE.PADCAL.bit.TRANSP = (*((uint32_t*) USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
91 USB->DEVICE.PADCAL.bit.TRANSN = (*((uint32_t*) USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
92 USB->DEVICE.PADCAL.bit.TRIM = (*((uint32_t*) USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
93
94 USB->DEVICE.QOSCTRL.bit.CQOS = 3; // High Quality
95 USB->DEVICE.QOSCTRL.bit.DQOS = 3; // High Quality
96
97 // Configure registers
98 USB->DEVICE.DESCADD.reg = (uint32_t) &sram_registers;
99 USB->DEVICE.CTRLB.reg = USB_DEVICE_CTRLB_SPDCONF_FS;
100 USB->DEVICE.CTRLA.reg = USB_CTRLA_MODE_DEVICE | USB_CTRLA_ENABLE | USB_CTRLA_RUNSTDBY;
101 while (USB->DEVICE.SYNCBUSY.bit.ENABLE == 1) {}
102
103 USB->DEVICE.INTFLAG.reg |= USB->DEVICE.INTFLAG.reg; // clear pending
104 USB->DEVICE.INTENSET.reg = /* USB_DEVICE_INTENSET_SOF | */ USB_DEVICE_INTENSET_EORST;
105
106 return true;
107}
108
109#if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X
110
111void dcd_int_enable(uint8_t rhport)
112{
113 (void) rhport;
114 NVIC_EnableIRQ(USB_0_IRQn);
115 NVIC_EnableIRQ(USB_1_IRQn);
116 NVIC_EnableIRQ(USB_2_IRQn);
117 NVIC_EnableIRQ(USB_3_IRQn);
118}
119
120void dcd_int_disable(uint8_t rhport)
121{
122 (void) rhport;
123 NVIC_DisableIRQ(USB_3_IRQn);
124 NVIC_DisableIRQ(USB_2_IRQn);
125 NVIC_DisableIRQ(USB_1_IRQn);
126 NVIC_DisableIRQ(USB_0_IRQn);
127}
128
129#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
130 CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21
131
132void dcd_int_enable(uint8_t rhport)
133{
134 (void) rhport;
135 NVIC_EnableIRQ(USB_IRQn);
136}
137
138void dcd_int_disable(uint8_t rhport)
139{
140 (void) rhport;
141 NVIC_DisableIRQ(USB_IRQn);
142}
143
144#else
145
146#error "No implementation available for dcd_int_enable / dcd_int_disable"
147
148#endif
149
150void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
151{
152 (void) dev_addr;
153
154 // Response with zlp status
155 dcd_edpt_xfer(rhport, 0x80, NULL, 0);
156
157 // DCD can only set address after status for this request is complete
158 // do it at dcd_edpt0_status_complete()
159
160 // Enable SUSPEND interrupt since the bus signal D+/D- are stable now.
161 USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTENCLR_SUSPEND; // clear pending
162 USB->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
163}
164
165void dcd_remote_wakeup(uint8_t rhport)
166{
167 (void) rhport;
168 USB->DEVICE.CTRLB.bit.UPRSM = 1;
169}
170
171// disconnect by disabling internal pull-up resistor on D+/D-
172void dcd_disconnect(uint8_t rhport)
173{
174 (void) rhport;
175 USB->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
176}
177
178// connect by enabling internal pull-up resistor on D+/D-
179void dcd_connect(uint8_t rhport)
180{
181 (void) rhport;
182 USB->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
183}
184
185void dcd_sof_enable(uint8_t rhport, bool en)
186{
187 (void) rhport;
188
189 if (en) {
190 USB->DEVICE.INTENSET.bit.SOF = 1;
191 } else {
192 USB->DEVICE.INTENCLR.bit.SOF = 1;
193 }
194}
195
196/*------------------------------------------------------------------*/
197/* DCD Endpoint port
198 *------------------------------------------------------------------*/
199
200// Invoked when a control transfer's status stage is complete.
201// May help DCD to prepare for next control transfer, this API is optional.
203{
204 (void) rhport;
205
209 {
210 uint8_t const dev_addr = (uint8_t) request->wValue;
211 USB->DEVICE.DADD.reg = USB_DEVICE_DADD_DADD(dev_addr) | USB_DEVICE_DADD_ADDEN;
212 }
213
214 // Just finished status stage, prepare for next setup packet
215 // Note: we may already prepare setup when queueing the control status.
216 // but it has no harm to do it again here
217 prepare_setup();
218}
219
220bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
221{
222 (void) rhport;
223
224 uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
225 uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
226
227 UsbDeviceDescBank* bank = &sram_registers[epnum][dir];
228 uint32_t size_value = 0;
229 while (size_value < 7) {
230 if (1 << (size_value + 3) >= tu_edpt_packet_size(desc_edpt)) {
231 break;
232 }
233 size_value++;
234 }
235
236 // unsupported endpoint size
237 if ( size_value == 7 && tu_edpt_packet_size(desc_edpt) > 1023 ) return false;
238
239 bank->PCKSIZE.bit.SIZE = size_value;
240
241 UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
242
243 if ( dir == TUSB_DIR_OUT )
244 {
245 ep->EPCFG.bit.EPTYPE0 = desc_edpt->bmAttributes.xfer + 1;
246 ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0 | USB_DEVICE_EPSTATUSCLR_DTGLOUT; // clear stall & dtoggle
247 ep->EPINTENSET.bit.TRCPT0 = true;
248 }else
249 {
250 ep->EPCFG.bit.EPTYPE1 = desc_edpt->bmAttributes.xfer + 1;
251 ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1 | USB_DEVICE_EPSTATUSCLR_DTGLIN; // clear stall & dtoggle
252 ep->EPINTENSET.bit.TRCPT1 = true;
253 }
254
255 return true;
256}
257
258void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) {
259 (void) rhport;
260 (void) ep_addr;
261
262 // TODO: implement if necessary?
263}
264
265void dcd_edpt_close_all (uint8_t rhport)
266{
267 (void) rhport;
268 // TODO implement dcd_edpt_close_all()
269}
270
271bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
272{
273 (void) rhport;
274
275 uint8_t const epnum = tu_edpt_number(ep_addr);
276 uint8_t const dir = tu_edpt_dir(ep_addr);
277
278 UsbDeviceDescBank* bank = &sram_registers[epnum][dir];
279 UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
280
281 bank->ADDR.reg = (uint32_t) buffer;
282
283 // A SETUP token can occur immediately after an ZLP Status.
284 // So make sure we have a valid buffer for setup packet.
285 // Status = ZLP EP0 with direction opposite to one in the dir bit of current setup
286 if ( (epnum == 0) && (buffer == NULL) && (total_bytes == 0) && (dir != tu_edpt_dir(_setup_packet[0])) ) {
287 prepare_setup();
288 }
289
290 if ( dir == TUSB_DIR_OUT )
291 {
292 bank->PCKSIZE.bit.MULTI_PACKET_SIZE = total_bytes;
293 bank->PCKSIZE.bit.BYTE_COUNT = 0;
294 ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
295 ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
296 } else
297 {
298 bank->PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
299 bank->PCKSIZE.bit.BYTE_COUNT = total_bytes;
300 ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
301 ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
302 }
303
304 return true;
305}
306
307void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
308{
309 (void) rhport;
310
311 uint8_t const epnum = tu_edpt_number(ep_addr);
312 UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
313
314 if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
315 ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
316 } else {
317 ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
318 }
319}
320
321void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
322{
323 (void) rhport;
324
325 uint8_t const epnum = tu_edpt_number(ep_addr);
326 UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
327
328 if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
329 ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1 | USB_DEVICE_EPSTATUSCLR_DTGLIN;
330 } else {
331 ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0 | USB_DEVICE_EPSTATUSCLR_DTGLOUT;
332 }
333}
334
335//--------------------------------------------------------------------+
336// Interrupt Handler
337//--------------------------------------------------------------------+
339 uint32_t epints = USB->DEVICE.EPINTSMRY.reg;
340
341 for (uint8_t epnum = 0; epnum < USB_EPT_NUM; epnum++) {
342 if ((epints & (1 << epnum)) == 0) {
343 continue;
344 }
345
346 UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
347 uint32_t epintflag = ep->EPINTFLAG.reg;
348
349 // Handle IN completions
350 if ((epintflag & USB_DEVICE_EPINTFLAG_TRCPT1) != 0) {
351 UsbDeviceDescBank* bank = &sram_registers[epnum][TUSB_DIR_IN];
352 uint16_t const total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT;
353
354 dcd_event_xfer_complete(0, epnum | TUSB_DIR_IN_MASK, total_transfer_size, XFER_RESULT_SUCCESS, true);
355
356 ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
357 }
358
359 // Handle OUT completions
360 if ((epintflag & USB_DEVICE_EPINTFLAG_TRCPT0) != 0) {
361 UsbDeviceDescBank* bank = &sram_registers[epnum][TUSB_DIR_OUT];
362 uint16_t const total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT;
363
364 dcd_event_xfer_complete(0, epnum, total_transfer_size, XFER_RESULT_SUCCESS, true);
365
366 ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
367 }
368 }
369}
370
371
372void dcd_int_handler (uint8_t rhport)
373{
374 (void) rhport;
375
376 uint32_t int_status = USB->DEVICE.INTFLAG.reg & USB->DEVICE.INTENSET.reg;
377
378 // Start of Frame
379 if ( int_status & USB_DEVICE_INTFLAG_SOF )
380 {
381 USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
382 const uint32_t frame = USB->DEVICE.FNUM.bit.FNUM;
383 dcd_event_sof(0, frame, true);
384 //dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
385 }
386
387 // SAMD doesn't distinguish between Suspend and Disconnect state.
388 // Both condition will cause SUSPEND interrupt triggered.
389 // To prevent being triggered when D+/D- are not stable, SUSPEND interrupt is only
390 // enabled when we received SET_ADDRESS request and cleared on Bus Reset
391 if ( int_status & USB_DEVICE_INTFLAG_SUSPEND )
392 {
393 USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
394
395 // Enable wakeup interrupt
396 USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; // clear pending
397 USB->DEVICE.INTENSET.reg = USB_DEVICE_INTFLAG_WAKEUP;
398
399 dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
400 }
401
402 // Wakeup interrupt is only enabled when we got suspended.
403 // Wakeup interrupt will disable itself
404 if ( int_status & USB_DEVICE_INTFLAG_WAKEUP )
405 {
406 USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
407
408 // disable wakeup interrupt itself
409 USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTFLAG_WAKEUP;
410 dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
411 }
412
413 // Enable of Reset
414 if ( int_status & USB_DEVICE_INTFLAG_EORST )
415 {
416 USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
417
418 // Disable both suspend and wakeup interrupt
419 USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_SUSPEND;
420
421 bus_reset();
423 }
424
425 // Handle SETUP packet
426 if (USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.bit.RXSTP)
427 {
428 // This copies the data elsewhere so we can reuse the buffer.
430
431 // Although Setup packet only set RXSTP bit,
432 // TRCPT0 bit could already be set by previous ZLP OUT Status (not handled until now).
433 // Since control status complete event is optional, we can just clear TRCPT0 and skip the status event
434 USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP | USB_DEVICE_EPINTFLAG_TRCPT0;
435 }
436
437 // Handle complete transfer
439}
440
441#endif
static TU_ATTR_ALWAYS_INLINE void dcd_event_bus_signal(uint8_t rhport, dcd_eventid_t eid, bool in_isr)
Definition: dcd.h:196
static TU_ATTR_ALWAYS_INLINE void dcd_event_xfer_complete(uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr)
Definition: dcd.h:222
static TU_ATTR_ALWAYS_INLINE void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr)
Definition: dcd.h:232
static TU_ATTR_ALWAYS_INLINE void dcd_event_setup_received(uint8_t rhport, uint8_t const *setup, bool in_isr)
Definition: dcd.h:213
static TU_ATTR_ALWAYS_INLINE void dcd_event_bus_reset(uint8_t rhport, tusb_speed_t speed, bool in_isr)
Definition: dcd.h:204
uint8_t _setup_packet[8]
uint16_t total_bytes
Definition: dcd_nuc505.c:113
uint8_t dev_addr
Definition: dcd_pic32mz.c:81
void maybe_transfer_complete(void)
Definition: dcd_samd.c:338
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
Definition: dcd_samd.c:307
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
Definition: dcd_samd.c:258
static void bus_reset(void)
Definition: dcd_samd.c:62
void dcd_int_handler(uint8_t rhport)
Definition: dcd_samd.c:372
void dcd_disconnect(uint8_t rhport)
Definition: dcd_samd.c:172
void dcd_edpt_close_all(uint8_t rhport)
Definition: dcd_samd.c:265
static TU_ATTR_ALIGNED(4)
Definition: dcd_samd.c:40
void dcd_int_disable(uint8_t rhport)
Definition: dcd_samd.c:120
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
Definition: dcd_samd.c:321
void dcd_connect(uint8_t rhport)
Definition: dcd_samd.c:179
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
Definition: dcd_samd.c:220
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
Definition: dcd_samd.c:271
void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request)
Definition: dcd_samd.c:202
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
Definition: dcd_samd.c:150
bool dcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init)
Definition: dcd_samd.c:81
void dcd_int_enable(uint8_t rhport)
Definition: dcd_samd.c:111
void dcd_remote_wakeup(uint8_t rhport)
Definition: dcd_samd.c:165
void dcd_sof_enable(uint8_t rhport, bool en)
Definition: dcd_samd.c:185
uint8_t const * buffer
Definition: midi_device.h:100
AUDIO Channel Cluster Descriptor (4.1)
Definition: audio.h:647
uint16_t wValue
Definition: audio.h:934
struct TU_ATTR_PACKED::@16::TU_ATTR_PACKED bmRequestType_bit
uint8_t bmAttributes
See: audio_clock_source_attribute_t.
Definition: audio.h:672
uint8_t bEndpointAddress
Definition: video.h:306
uint8_t bRequest
Request type audio_cs_req_t.
Definition: audio.h:831
@ TUSB_DIR_IN
Definition: tusb_types.h:67
@ TUSB_DIR_OUT
Definition: tusb_types.h:66
@ TUSB_DIR_IN_MASK
Definition: tusb_types.h:69
@ TUSB_REQ_SET_ADDRESS
Definition: tusb_types.h:127
@ TUSB_SPEED_FULL
Definition: tusb_types.h:50
struct TU_ATTR_PACKED tusb_control_request_t
static TU_ATTR_ALWAYS_INLINE uint8_t tu_edpt_number(uint8_t addr)
Definition: tusb_types.h:507
@ XFER_RESULT_SUCCESS
Definition: tusb_types.h:237
@ TUSB_REQ_RCPT_DEVICE
Definition: tusb_types.h:151
static TU_ATTR_ALWAYS_INLINE uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const *desc_ep)
Definition: tusb_types.h:515
TU_ATTR_PACKED_END TU_ATTR_BIT_FIELD_ORDER_END static TU_ATTR_ALWAYS_INLINE tusb_dir_t tu_edpt_dir(uint8_t addr)
Definition: tusb_types.h:502
@ TUSB_REQ_TYPE_STANDARD
Definition: tusb_types.h:144
CFG_TUH_MEM_ALIGN tusb_control_request_t request
Definition: usbh.c:259