OpenFFBoard/doxygen/common__usb__regs_8h_source.html

 /*

* The MIT License (MIT)

*

* Copyright (c) 2019 Microchip Technology Inc.

* Copyright (c) 2018, hathach (tinyusb.org)

* Copyright (c) 2021, HiFiPhile

*

* Permission is hereby granted, free of charge, to any person obtaining a copy

* of this software and associated documentation files (the "Software"), to deal

* in the Software without restriction, including without limitation the rights

* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

* copies of the Software, and to permit persons to whom the Software is

* furnished to do so, subject to the following conditions:

*

* The above copyright notice and this permission notice shall be included in

* all copies or substantial portions of the Software.

*

* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

* THE SOFTWARE.

*

* This file is part of the TinyUSB stack.

*/


#ifndef _COMMON_USB_REGS_H_

#define _COMMON_USB_REGS_H_


#if CFG_TUSB_MCU == OPT_MCU_SAMX7X


/* -------- DEVDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Device DMA Channel Next Descriptor Address Register -------- */


#define DEVDMANXTDSC_OFFSET           (0x00)

#define DEVDMANXTDSC_NXT_DSC_ADD_Pos  0

#define DEVDMANXTDSC_NXT_DSC_ADD      (_U_(0xFFFFFFFF) << DEVDMANXTDSC_NXT_DSC_ADD_Pos)

#define DEVDMANXTDSC_Msk              _U_(0xFFFFFFFF)

/* -------- DEVDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Device DMA Channel Address Register -------- */


#define DEVDMAADDRESS_OFFSET          (0x04)

#define DEVDMAADDRESS_BUFF_ADD_Pos    0

#define DEVDMAADDRESS_BUFF_ADD        (_U_(0xFFFFFFFF) << DEVDMAADDRESS_BUFF_ADD_Pos)

#define DEVDMAADDRESS_Msk             _U_(0xFFFFFFFF)

/* -------- DEVDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Device DMA Channel Control Register -------- */


#define DEVDMACONTROL_OFFSET          (0x08)

#define DEVDMACONTROL_CHANN_ENB_Pos   0

#define DEVDMACONTROL_CHANN_ENB       (_U_(0x1) << DEVDMACONTROL_CHANN_ENB_Pos)

#define DEVDMACONTROL_LDNXT_DSC_Pos   1

#define DEVDMACONTROL_LDNXT_DSC       (_U_(0x1) << DEVDMACONTROL_LDNXT_DSC_Pos)

#define DEVDMACONTROL_END_TR_EN_Pos   2

#define DEVDMACONTROL_END_TR_EN       (_U_(0x1) << DEVDMACONTROL_END_TR_EN_Pos)

#define DEVDMACONTROL_END_B_EN_Pos    3

#define DEVDMACONTROL_END_B_EN        (_U_(0x1) << DEVDMACONTROL_END_B_EN_Pos)

#define DEVDMACONTROL_END_TR_IT_Pos   4

#define DEVDMACONTROL_END_TR_IT       (_U_(0x1) << DEVDMACONTROL_END_TR_IT_Pos)

#define DEVDMACONTROL_END_BUFFIT_Pos  5

#define DEVDMACONTROL_END_BUFFIT      (_U_(0x1) << DEVDMACONTROL_END_BUFFIT_Pos)

#define DEVDMACONTROL_DESC_LD_IT_Pos  6

#define DEVDMACONTROL_DESC_LD_IT      (_U_(0x1) << DEVDMACONTROL_DESC_LD_IT_Pos)

#define DEVDMACONTROL_BURST_LCK_Pos   7

#define DEVDMACONTROL_BURST_LCK       (_U_(0x1) << DEVDMACONTROL_BURST_LCK_Pos)

#define DEVDMACONTROL_BUFF_LENGTH_Pos 16

#define DEVDMACONTROL_BUFF_LENGTH     (_U_(0xFFFF) << DEVDMACONTROL_BUFF_LENGTH_Pos)

#define DEVDMACONTROL_Msk             _U_(0xFFFF00FF)

/* -------- DEVDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Device DMA Channel Status Register -------- */


#define DEVDMASTATUS_OFFSET           (0x0C)

#define DEVDMASTATUS_CHANN_ENB_Pos    0

#define DEVDMASTATUS_CHANN_ENB        (_U_(0x1) << DEVDMASTATUS_CHANN_ENB_Pos)

#define DEVDMASTATUS_CHANN_ACT_Pos    1

#define DEVDMASTATUS_CHANN_ACT        (_U_(0x1) << DEVDMASTATUS_CHANN_ACT_Pos)

#define DEVDMASTATUS_END_TR_ST_Pos    4

#define DEVDMASTATUS_END_TR_ST        (_U_(0x1) << DEVDMASTATUS_END_TR_ST_Pos)

#define DEVDMASTATUS_END_BF_ST_Pos    5

#define DEVDMASTATUS_END_BF_ST        (_U_(0x1) << DEVDMASTATUS_END_BF_ST_Pos)

#define DEVDMASTATUS_DESC_LDST_Pos    6

#define DEVDMASTATUS_DESC_LDST        (_U_(0x1) << DEVDMASTATUS_DESC_LDST_Pos)

#define DEVDMASTATUS_BUFF_COUNT_Pos   16

#define DEVDMASTATUS_BUFF_COUNT       (_U_(0xFFFF) << DEVDMASTATUS_BUFF_COUNT_Pos)

#define DEVDMASTATUS_Msk              _U_(0xFFFF0073)

/* -------- HSTDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Host DMA Channel Next Descriptor Address Register -------- */


#define HSTDMANXTDSC_OFFSET           (0x00)

#define HSTDMANXTDSC_NXT_DSC_ADD_Pos  0

#define HSTDMANXTDSC_NXT_DSC_ADD      (_U_(0xFFFFFFFF) << HSTDMANXTDSC_NXT_DSC_ADD_Pos)

#define HSTDMANXTDSC_Msk              _U_(0xFFFFFFFF)

/* -------- HSTDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Host DMA Channel Address Register -------- */


#define HSTDMAADDRESS_OFFSET          (0x04)

#define HSTDMAADDRESS_BUFF_ADD_Pos    0

#define HSTDMAADDRESS_BUFF_ADD        (_U_(0xFFFFFFFF) << HSTDMAADDRESS_BUFF_ADD_Pos)

#define HSTDMAADDRESS_Msk             _U_(0xFFFFFFFF)

/* -------- HSTDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Host DMA Channel Control Register -------- */


#define HSTDMACONTROL_OFFSET          (0x08)

#define HSTDMACONTROL_CHANN_ENB_Pos   0

#define HSTDMACONTROL_CHANN_ENB       (_U_(0x1) << HSTDMACONTROL_CHANN_ENB_Pos)

#define HSTDMACONTROL_LDNXT_DSC_Pos   1

#define HSTDMACONTROL_LDNXT_DSC       (_U_(0x1) << HSTDMACONTROL_LDNXT_DSC_Pos)

#define HSTDMACONTROL_END_TR_EN_Pos   2

#define HSTDMACONTROL_END_TR_EN       (_U_(0x1) << HSTDMACONTROL_END_TR_EN_Pos)

#define HSTDMACONTROL_END_B_EN_Pos    3

#define HSTDMACONTROL_END_B_EN        (_U_(0x1) << HSTDMACONTROL_END_B_EN_Pos)

#define HSTDMACONTROL_END_TR_IT_Pos   4

#define HSTDMACONTROL_END_TR_IT       (_U_(0x1) << HSTDMACONTROL_END_TR_IT_Pos)

#define HSTDMACONTROL_END_BUFFIT_Pos  5

#define HSTDMACONTROL_END_BUFFIT      (_U_(0x1) << HSTDMACONTROL_END_BUFFIT_Pos)

#define HSTDMACONTROL_DESC_LD_IT_Pos  6

#define HSTDMACONTROL_DESC_LD_IT      (_U_(0x1) << HSTDMACONTROL_DESC_LD_IT_Pos)

#define HSTDMACONTROL_BURST_LCK_Pos   7

#define HSTDMACONTROL_BURST_LCK       (_U_(0x1) << HSTDMACONTROL_BURST_LCK_Pos)

#define HSTDMACONTROL_BUFF_LENGTH_Pos 16

#define HSTDMACONTROL_BUFF_LENGTH     (_U_(0xFFFF) << HSTDMACONTROL_BUFF_LENGTH_Pos)

#define HSTDMACONTROL_Msk             _U_(0xFFFF00FF)

/* -------- HSTDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Host DMA Channel Status Register -------- */


#define HSTDMASTATUS_OFFSET           (0x0C)

#define HSTDMASTATUS_CHANN_ENB_Pos    0

#define HSTDMASTATUS_CHANN_ENB        (_U_(0x1) << HSTDMASTATUS_CHANN_ENB_Pos)

#define HSTDMASTATUS_CHANN_ACT_Pos    1

#define HSTDMASTATUS_CHANN_ACT        (_U_(0x1) << HSTDMASTATUS_CHANN_ACT_Pos)

#define HSTDMASTATUS_END_TR_ST_Pos    4

#define HSTDMASTATUS_END_TR_ST        (_U_(0x1) << HSTDMASTATUS_END_TR_ST_Pos)

#define HSTDMASTATUS_END_BF_ST_Pos    5

#define HSTDMASTATUS_END_BF_ST        (_U_(0x1) << HSTDMASTATUS_END_BF_ST_Pos)

#define HSTDMASTATUS_DESC_LDST_Pos    6

#define HSTDMASTATUS_DESC_LDST        (_U_(0x1) << HSTDMASTATUS_DESC_LDST_Pos)

#define HSTDMASTATUS_BUFF_COUNT_Pos   16

#define HSTDMASTATUS_BUFF_COUNT       (_U_(0xFFFF) << HSTDMASTATUS_BUFF_COUNT_Pos)

#define HSTDMASTATUS_Msk              _U_(0xFFFF0073)

/* -------- DEVCTRL : (USBHS Offset: 0x00) (R/W 32) Device General Control Register -------- */


#define DEVCTRL_OFFSET                (0x00)

#define DEVCTRL_UADD_Pos              0

#define DEVCTRL_UADD                  (_U_(0x7F) << DEVCTRL_UADD_Pos)

#define DEVCTRL_ADDEN_Pos             7

#define DEVCTRL_ADDEN                 (_U_(0x1) << DEVCTRL_ADDEN_Pos)

#define DEVCTRL_DETACH_Pos            8

#define DEVCTRL_DETACH                (_U_(0x1) << DEVCTRL_DETACH_Pos)

#define DEVCTRL_RMWKUP_Pos            9

#define DEVCTRL_RMWKUP                (_U_(0x1) << DEVCTRL_RMWKUP_Pos)

#define DEVCTRL_SPDCONF_Pos           10

#define DEVCTRL_SPDCONF               (_U_(0x3) << DEVCTRL_SPDCONF_Pos)

#define   DEVCTRL_SPDCONF_NORMAL_Val  _U_(0x0)

#define   DEVCTRL_SPDCONF_LOW_POWER_Val _U_(0x1)

#define   DEVCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2)

#define   DEVCTRL_SPDCONF_FORCED_FS_Val _U_(0x3)

#define DEVCTRL_SPDCONF_NORMAL        (DEVCTRL_SPDCONF_NORMAL_Val << DEVCTRL_SPDCONF_Pos)

#define DEVCTRL_SPDCONF_LOW_POWER     (DEVCTRL_SPDCONF_LOW_POWER_Val << DEVCTRL_SPDCONF_Pos)

#define DEVCTRL_SPDCONF_HIGH_SPEED    (DEVCTRL_SPDCONF_HIGH_SPEED_Val << DEVCTRL_SPDCONF_Pos)

#define DEVCTRL_SPDCONF_FORCED_FS     (DEVCTRL_SPDCONF_FORCED_FS_Val << DEVCTRL_SPDCONF_Pos)

#define DEVCTRL_LS_Pos                12

#define DEVCTRL_LS                    (_U_(0x1) << DEVCTRL_LS_Pos)

#define DEVCTRL_TSTJ_Pos              13

#define DEVCTRL_TSTJ                  (_U_(0x1) << DEVCTRL_TSTJ_Pos)

#define DEVCTRL_TSTK_Pos              14

#define DEVCTRL_TSTK                  (_U_(0x1) << DEVCTRL_TSTK_Pos)

#define DEVCTRL_TSTPCKT_Pos           15

#define DEVCTRL_TSTPCKT               (_U_(0x1) << DEVCTRL_TSTPCKT_Pos)

#define DEVCTRL_OPMODE2_Pos           16

#define DEVCTRL_OPMODE2               (_U_(0x1) << DEVCTRL_OPMODE2_Pos)

#define DEVCTRL_Msk                   _U_(0x1FFFF)

#define DEVCTRL_OPMODE_Pos            16

#define DEVCTRL_OPMODE                (_U_(0x1) << DEVCTRL_OPMODE_Pos)

/* -------- DEVISR : (USBHS Offset: 0x04) (R/ 32) Device Global Interrupt Status Register -------- */


#define DEVISR_OFFSET                 (0x04)

#define DEVISR_SUSP_Pos               0

#define DEVISR_SUSP                   (_U_(0x1) << DEVISR_SUSP_Pos)

#define DEVISR_MSOF_Pos               1

#define DEVISR_MSOF                   (_U_(0x1) << DEVISR_MSOF_Pos)

#define DEVISR_SOF_Pos                2

#define DEVISR_SOF                    (_U_(0x1) << DEVISR_SOF_Pos)

#define DEVISR_EORST_Pos              3

#define DEVISR_EORST                  (_U_(0x1) << DEVISR_EORST_Pos)

#define DEVISR_WAKEUP_Pos             4

#define DEVISR_WAKEUP                 (_U_(0x1) << DEVISR_WAKEUP_Pos)

#define DEVISR_EORSM_Pos              5

#define DEVISR_EORSM                  (_U_(0x1) << DEVISR_EORSM_Pos)

#define DEVISR_UPRSM_Pos              6

#define DEVISR_UPRSM                  (_U_(0x1) << DEVISR_UPRSM_Pos)

#define DEVISR_PEP_0_Pos              12

#define DEVISR_PEP_0                  (_U_(0x1) << DEVISR_PEP_0_Pos)

#define DEVISR_PEP_1_Pos              13

#define DEVISR_PEP_1                  (_U_(0x1) << DEVISR_PEP_1_Pos)

#define DEVISR_PEP_2_Pos              14

#define DEVISR_PEP_2                  (_U_(0x1) << DEVISR_PEP_2_Pos)

#define DEVISR_PEP_3_Pos              15

#define DEVISR_PEP_3                  (_U_(0x1) << DEVISR_PEP_3_Pos)

#define DEVISR_PEP_4_Pos              16

#define DEVISR_PEP_4                  (_U_(0x1) << DEVISR_PEP_4_Pos)

#define DEVISR_PEP_5_Pos              17

#define DEVISR_PEP_5                  (_U_(0x1) << DEVISR_PEP_5_Pos)

#define DEVISR_PEP_6_Pos              18

#define DEVISR_PEP_6                  (_U_(0x1) << DEVISR_PEP_6_Pos)

#define DEVISR_PEP_7_Pos              19

#define DEVISR_PEP_7                  (_U_(0x1) << DEVISR_PEP_7_Pos)

#define DEVISR_PEP_8_Pos              20

#define DEVISR_PEP_8                  (_U_(0x1) << DEVISR_PEP_8_Pos)

#define DEVISR_PEP_9_Pos              21

#define DEVISR_PEP_9                  (_U_(0x1) << DEVISR_PEP_9_Pos)

#define DEVISR_DMA_1_Pos              25

#define DEVISR_DMA_1                  (_U_(0x1) << DEVISR_DMA_1_Pos)

#define DEVISR_DMA_2_Pos              26

#define DEVISR_DMA_2                  (_U_(0x1) << DEVISR_DMA_2_Pos)

#define DEVISR_DMA_3_Pos              27

#define DEVISR_DMA_3                  (_U_(0x1) << DEVISR_DMA_3_Pos)

#define DEVISR_DMA_4_Pos              28

#define DEVISR_DMA_4                  (_U_(0x1) << DEVISR_DMA_4_Pos)

#define DEVISR_DMA_5_Pos              29

#define DEVISR_DMA_5                  (_U_(0x1) << DEVISR_DMA_5_Pos)

#define DEVISR_DMA_6_Pos              30

#define DEVISR_DMA_6                  (_U_(0x1) << DEVISR_DMA_6_Pos)

#define DEVISR_DMA_7_Pos              31

#define DEVISR_DMA_7                  (_U_(0x1) << DEVISR_DMA_7_Pos)

#define DEVISR_Msk                    _U_(0xFE3FF07F)

#define DEVISR_PEP__Pos               12

#define DEVISR_PEP_                   (_U_(0x3FF) << DEVISR_PEP__Pos)

#define DEVISR_DMA__Pos               25

#define DEVISR_DMA_                   (_U_(0x7F) << DEVISR_DMA__Pos)

/* -------- DEVICR : (USBHS Offset: 0x08) (/W 32) Device Global Interrupt Clear Register -------- */


#define DEVICR_OFFSET                 (0x08)

#define DEVICR_SUSPC_Pos              0

#define DEVICR_SUSPC                  (_U_(0x1) << DEVICR_SUSPC_Pos)

#define DEVICR_MSOFC_Pos              1

#define DEVICR_MSOFC                  (_U_(0x1) << DEVICR_MSOFC_Pos)

#define DEVICR_SOFC_Pos               2

#define DEVICR_SOFC                   (_U_(0x1) << DEVICR_SOFC_Pos)

#define DEVICR_EORSTC_Pos             3

#define DEVICR_EORSTC                 (_U_(0x1) << DEVICR_EORSTC_Pos)

#define DEVICR_WAKEUPC_Pos            4

#define DEVICR_WAKEUPC                (_U_(0x1) << DEVICR_WAKEUPC_Pos)

#define DEVICR_EORSMC_Pos             5

#define DEVICR_EORSMC                 (_U_(0x1) << DEVICR_EORSMC_Pos)

#define DEVICR_UPRSMC_Pos             6

#define DEVICR_UPRSMC                 (_U_(0x1) << DEVICR_UPRSMC_Pos)

#define DEVICR_Msk                    _U_(0x7F)

/* -------- DEVIFR : (USBHS Offset: 0x0c) (/W 32) Device Global Interrupt Set Register -------- */


#define DEVIFR_OFFSET                 (0x0C)

#define DEVIFR_SUSPS_Pos              0

#define DEVIFR_SUSPS                  (_U_(0x1) << DEVIFR_SUSPS_Pos)

#define DEVIFR_MSOFS_Pos              1

#define DEVIFR_MSOFS                  (_U_(0x1) << DEVIFR_MSOFS_Pos)

#define DEVIFR_SOFS_Pos               2

#define DEVIFR_SOFS                   (_U_(0x1) << DEVIFR_SOFS_Pos)

#define DEVIFR_EORSTS_Pos             3

#define DEVIFR_EORSTS                 (_U_(0x1) << DEVIFR_EORSTS_Pos)

#define DEVIFR_WAKEUPS_Pos            4

#define DEVIFR_WAKEUPS                (_U_(0x1) << DEVIFR_WAKEUPS_Pos)

#define DEVIFR_EORSMS_Pos             5

#define DEVIFR_EORSMS                 (_U_(0x1) << DEVIFR_EORSMS_Pos)

#define DEVIFR_UPRSMS_Pos             6

#define DEVIFR_UPRSMS                 (_U_(0x1) << DEVIFR_UPRSMS_Pos)

#define DEVIFR_DMA_1_Pos              25

#define DEVIFR_DMA_1                  (_U_(0x1) << DEVIFR_DMA_1_Pos)

#define DEVIFR_DMA_2_Pos              26

#define DEVIFR_DMA_2                  (_U_(0x1) << DEVIFR_DMA_2_Pos)

#define DEVIFR_DMA_3_Pos              27

#define DEVIFR_DMA_3                  (_U_(0x1) << DEVIFR_DMA_3_Pos)

#define DEVIFR_DMA_4_Pos              28

#define DEVIFR_DMA_4                  (_U_(0x1) << DEVIFR_DMA_4_Pos)

#define DEVIFR_DMA_5_Pos              29

#define DEVIFR_DMA_5                  (_U_(0x1) << DEVIFR_DMA_5_Pos)

#define DEVIFR_DMA_6_Pos              30

#define DEVIFR_DMA_6                  (_U_(0x1) << DEVIFR_DMA_6_Pos)

#define DEVIFR_DMA_7_Pos              31

#define DEVIFR_DMA_7                  (_U_(0x1) << DEVIFR_DMA_7_Pos)

#define DEVIFR_Msk                    _U_(0xFE00007F)

#define DEVIFR_DMA__Pos               25

#define DEVIFR_DMA_                   (_U_(0x7F) << DEVIFR_DMA__Pos)

/* -------- DEVIMR : (USBHS Offset: 0x10) (R/ 32) Device Global Interrupt Mask Register -------- */


#define DEVIMR_OFFSET                 (0x10)

#define DEVIMR_SUSPE_Pos              0

#define DEVIMR_SUSPE                  (_U_(0x1) << DEVIMR_SUSPE_Pos)

#define DEVIMR_MSOFE_Pos              1

#define DEVIMR_MSOFE                  (_U_(0x1) << DEVIMR_MSOFE_Pos)

#define DEVIMR_SOFE_Pos               2

#define DEVIMR_SOFE                   (_U_(0x1) << DEVIMR_SOFE_Pos)

#define DEVIMR_EORSTE_Pos             3

#define DEVIMR_EORSTE                 (_U_(0x1) << DEVIMR_EORSTE_Pos)

#define DEVIMR_WAKEUPE_Pos            4

#define DEVIMR_WAKEUPE                (_U_(0x1) << DEVIMR_WAKEUPE_Pos)

#define DEVIMR_EORSME_Pos             5

#define DEVIMR_EORSME                 (_U_(0x1) << DEVIMR_EORSME_Pos)

#define DEVIMR_UPRSME_Pos             6

#define DEVIMR_UPRSME                 (_U_(0x1) << DEVIMR_UPRSME_Pos)

#define DEVIMR_PEP_0_Pos              12

#define DEVIMR_PEP_0                  (_U_(0x1) << DEVIMR_PEP_0_Pos)

#define DEVIMR_PEP_1_Pos              13

#define DEVIMR_PEP_1                  (_U_(0x1) << DEVIMR_PEP_1_Pos)

#define DEVIMR_PEP_2_Pos              14

#define DEVIMR_PEP_2                  (_U_(0x1) << DEVIMR_PEP_2_Pos)

#define DEVIMR_PEP_3_Pos              15

#define DEVIMR_PEP_3                  (_U_(0x1) << DEVIMR_PEP_3_Pos)

#define DEVIMR_PEP_4_Pos              16

#define DEVIMR_PEP_4                  (_U_(0x1) << DEVIMR_PEP_4_Pos)

#define DEVIMR_PEP_5_Pos              17

#define DEVIMR_PEP_5                  (_U_(0x1) << DEVIMR_PEP_5_Pos)

#define DEVIMR_PEP_6_Pos              18

#define DEVIMR_PEP_6                  (_U_(0x1) << DEVIMR_PEP_6_Pos)

#define DEVIMR_PEP_7_Pos              19

#define DEVIMR_PEP_7                  (_U_(0x1) << DEVIMR_PEP_7_Pos)

#define DEVIMR_PEP_8_Pos              20

#define DEVIMR_PEP_8                  (_U_(0x1) << DEVIMR_PEP_8_Pos)

#define DEVIMR_PEP_9_Pos              21

#define DEVIMR_PEP_9                  (_U_(0x1) << DEVIMR_PEP_9_Pos)

#define DEVIMR_DMA_1_Pos              25

#define DEVIMR_DMA_1                  (_U_(0x1) << DEVIMR_DMA_1_Pos)

#define DEVIMR_DMA_2_Pos              26

#define DEVIMR_DMA_2                  (_U_(0x1) << DEVIMR_DMA_2_Pos)

#define DEVIMR_DMA_3_Pos              27

#define DEVIMR_DMA_3                  (_U_(0x1) << DEVIMR_DMA_3_Pos)

#define DEVIMR_DMA_4_Pos              28

#define DEVIMR_DMA_4                  (_U_(0x1) << DEVIMR_DMA_4_Pos)

#define DEVIMR_DMA_5_Pos              29

#define DEVIMR_DMA_5                  (_U_(0x1) << DEVIMR_DMA_5_Pos)

#define DEVIMR_DMA_6_Pos              30

#define DEVIMR_DMA_6                  (_U_(0x1) << DEVIMR_DMA_6_Pos)

#define DEVIMR_DMA_7_Pos              31

#define DEVIMR_DMA_7                  (_U_(0x1) << DEVIMR_DMA_7_Pos)

#define DEVIMR_Msk                    _U_(0xFE3FF07F)

#define DEVIMR_PEP__Pos               12

#define DEVIMR_PEP_                   (_U_(0x3FF) << DEVIMR_PEP__Pos)

#define DEVIMR_DMA__Pos               25

#define DEVIMR_DMA_                   (_U_(0x7F) << DEVIMR_DMA__Pos)

/* -------- DEVIDR : (USBHS Offset: 0x14) (/W 32) Device Global Interrupt Disable Register -------- */


#define DEVIDR_OFFSET                 (0x14)

#define DEVIDR_SUSPEC_Pos             0

#define DEVIDR_SUSPEC                 (_U_(0x1) << DEVIDR_SUSPEC_Pos)

#define DEVIDR_MSOFEC_Pos             1

#define DEVIDR_MSOFEC                 (_U_(0x1) << DEVIDR_MSOFEC_Pos)

#define DEVIDR_SOFEC_Pos              2

#define DEVIDR_SOFEC                  (_U_(0x1) << DEVIDR_SOFEC_Pos)

#define DEVIDR_EORSTEC_Pos            3

#define DEVIDR_EORSTEC                (_U_(0x1) << DEVIDR_EORSTEC_Pos)

#define DEVIDR_WAKEUPEC_Pos           4

#define DEVIDR_WAKEUPEC               (_U_(0x1) << DEVIDR_WAKEUPEC_Pos)

#define DEVIDR_EORSMEC_Pos            5

#define DEVIDR_EORSMEC                (_U_(0x1) << DEVIDR_EORSMEC_Pos)

#define DEVIDR_UPRSMEC_Pos            6

#define DEVIDR_UPRSMEC                (_U_(0x1) << DEVIDR_UPRSMEC_Pos)

#define DEVIDR_PEP_0_Pos              12

#define DEVIDR_PEP_0                  (_U_(0x1) << DEVIDR_PEP_0_Pos)

#define DEVIDR_PEP_1_Pos              13

#define DEVIDR_PEP_1                  (_U_(0x1) << DEVIDR_PEP_1_Pos)

#define DEVIDR_PEP_2_Pos              14

#define DEVIDR_PEP_2                  (_U_(0x1) << DEVIDR_PEP_2_Pos)

#define DEVIDR_PEP_3_Pos              15

#define DEVIDR_PEP_3                  (_U_(0x1) << DEVIDR_PEP_3_Pos)

#define DEVIDR_PEP_4_Pos              16

#define DEVIDR_PEP_4                  (_U_(0x1) << DEVIDR_PEP_4_Pos)

#define DEVIDR_PEP_5_Pos              17

#define DEVIDR_PEP_5                  (_U_(0x1) << DEVIDR_PEP_5_Pos)

#define DEVIDR_PEP_6_Pos              18

#define DEVIDR_PEP_6                  (_U_(0x1) << DEVIDR_PEP_6_Pos)

#define DEVIDR_PEP_7_Pos              19

#define DEVIDR_PEP_7                  (_U_(0x1) << DEVIDR_PEP_7_Pos)

#define DEVIDR_PEP_8_Pos              20

#define DEVIDR_PEP_8                  (_U_(0x1) << DEVIDR_PEP_8_Pos)

#define DEVIDR_PEP_9_Pos              21

#define DEVIDR_PEP_9                  (_U_(0x1) << DEVIDR_PEP_9_Pos)

#define DEVIDR_DMA_1_Pos              25

#define DEVIDR_DMA_1                  (_U_(0x1) << DEVIDR_DMA_1_Pos)

#define DEVIDR_DMA_2_Pos              26

#define DEVIDR_DMA_2                  (_U_(0x1) << DEVIDR_DMA_2_Pos)

#define DEVIDR_DMA_3_Pos              27

#define DEVIDR_DMA_3                  (_U_(0x1) << DEVIDR_DMA_3_Pos)

#define DEVIDR_DMA_4_Pos              28

#define DEVIDR_DMA_4                  (_U_(0x1) << DEVIDR_DMA_4_Pos)

#define DEVIDR_DMA_5_Pos              29

#define DEVIDR_DMA_5                  (_U_(0x1) << DEVIDR_DMA_5_Pos)

#define DEVIDR_DMA_6_Pos              30

#define DEVIDR_DMA_6                  (_U_(0x1) << DEVIDR_DMA_6_Pos)

#define DEVIDR_DMA_7_Pos              31

#define DEVIDR_DMA_7                  (_U_(0x1) << DEVIDR_DMA_7_Pos)

#define DEVIDR_Msk                    _U_(0xFE3FF07F)

#define DEVIDR_PEP__Pos               12

#define DEVIDR_PEP_                   (_U_(0x3FF) << DEVIDR_PEP__Pos)

#define DEVIDR_DMA__Pos               25

#define DEVIDR_DMA_                   (_U_(0x7F) << DEVIDR_DMA__Pos)

/* -------- DEVIER : (USBHS Offset: 0x18) (/W 32) Device Global Interrupt Enable Register -------- */


#define DEVIER_OFFSET                 (0x18)

#define DEVIER_SUSPES_Pos             0

#define DEVIER_SUSPES                 (_U_(0x1) << DEVIER_SUSPES_Pos)

#define DEVIER_MSOFES_Pos             1

#define DEVIER_MSOFES                 (_U_(0x1) << DEVIER_MSOFES_Pos)

#define DEVIER_SOFES_Pos              2

#define DEVIER_SOFES                  (_U_(0x1) << DEVIER_SOFES_Pos)

#define DEVIER_EORSTES_Pos            3

#define DEVIER_EORSTES                (_U_(0x1) << DEVIER_EORSTES_Pos)

#define DEVIER_WAKEUPES_Pos           4

#define DEVIER_WAKEUPES               (_U_(0x1) << DEVIER_WAKEUPES_Pos)

#define DEVIER_EORSMES_Pos            5

#define DEVIER_EORSMES                (_U_(0x1) << DEVIER_EORSMES_Pos)

#define DEVIER_UPRSMES_Pos            6

#define DEVIER_UPRSMES                (_U_(0x1) << DEVIER_UPRSMES_Pos)

#define DEVIER_PEP_0_Pos              12

#define DEVIER_PEP_0                  (_U_(0x1) << DEVIER_PEP_0_Pos)

#define DEVIER_PEP_1_Pos              13

#define DEVIER_PEP_1                  (_U_(0x1) << DEVIER_PEP_1_Pos)

#define DEVIER_PEP_2_Pos              14

#define DEVIER_PEP_2                  (_U_(0x1) << DEVIER_PEP_2_Pos)

#define DEVIER_PEP_3_Pos              15

#define DEVIER_PEP_3                  (_U_(0x1) << DEVIER_PEP_3_Pos)

#define DEVIER_PEP_4_Pos              16

#define DEVIER_PEP_4                  (_U_(0x1) << DEVIER_PEP_4_Pos)

#define DEVIER_PEP_5_Pos              17

#define DEVIER_PEP_5                  (_U_(0x1) << DEVIER_PEP_5_Pos)

#define DEVIER_PEP_6_Pos              18

#define DEVIER_PEP_6                  (_U_(0x1) << DEVIER_PEP_6_Pos)

#define DEVIER_PEP_7_Pos              19

#define DEVIER_PEP_7                  (_U_(0x1) << DEVIER_PEP_7_Pos)

#define DEVIER_PEP_8_Pos              20

#define DEVIER_PEP_8                  (_U_(0x1) << DEVIER_PEP_8_Pos)

#define DEVIER_PEP_9_Pos              21

#define DEVIER_PEP_9                  (_U_(0x1) << DEVIER_PEP_9_Pos)

#define DEVIER_DMA_1_Pos              25

#define DEVIER_DMA_1                  (_U_(0x1) << DEVIER_DMA_1_Pos)

#define DEVIER_DMA_2_Pos              26

#define DEVIER_DMA_2                  (_U_(0x1) << DEVIER_DMA_2_Pos)

#define DEVIER_DMA_3_Pos              27

#define DEVIER_DMA_3                  (_U_(0x1) << DEVIER_DMA_3_Pos)

#define DEVIER_DMA_4_Pos              28

#define DEVIER_DMA_4                  (_U_(0x1) << DEVIER_DMA_4_Pos)

#define DEVIER_DMA_5_Pos              29

#define DEVIER_DMA_5                  (_U_(0x1) << DEVIER_DMA_5_Pos)

#define DEVIER_DMA_6_Pos              30

#define DEVIER_DMA_6                  (_U_(0x1) << DEVIER_DMA_6_Pos)

#define DEVIER_DMA_7_Pos              31

#define DEVIER_DMA_7                  (_U_(0x1) << DEVIER_DMA_7_Pos)

#define DEVIER_Msk                    _U_(0xFE3FF07F)

#define DEVIER_PEP__Pos               12

#define DEVIER_PEP_                   (_U_(0x3FF) << DEVIER_PEP__Pos)

#define DEVIER_DMA__Pos               25

#define DEVIER_DMA_                   (_U_(0x7F) << DEVIER_DMA__Pos)

/* -------- DEVEPT : (USBHS Offset: 0x1c) (R/W 32) Device Endpoint Register -------- */


#define DEVEPT_OFFSET                 (0x1C)

#define DEVEPT_EPEN0_Pos              0

#define DEVEPT_EPEN0                  (_U_(0x1) << DEVEPT_EPEN0_Pos)

#define DEVEPT_EPEN1_Pos              1

#define DEVEPT_EPEN1                  (_U_(0x1) << DEVEPT_EPEN1_Pos)

#define DEVEPT_EPEN2_Pos              2

#define DEVEPT_EPEN2                  (_U_(0x1) << DEVEPT_EPEN2_Pos)

#define DEVEPT_EPEN3_Pos              3

#define DEVEPT_EPEN3                  (_U_(0x1) << DEVEPT_EPEN3_Pos)

#define DEVEPT_EPEN4_Pos              4

#define DEVEPT_EPEN4                  (_U_(0x1) << DEVEPT_EPEN4_Pos)

#define DEVEPT_EPEN5_Pos              5

#define DEVEPT_EPEN5                  (_U_(0x1) << DEVEPT_EPEN5_Pos)

#define DEVEPT_EPEN6_Pos              6

#define DEVEPT_EPEN6                  (_U_(0x1) << DEVEPT_EPEN6_Pos)

#define DEVEPT_EPEN7_Pos              7

#define DEVEPT_EPEN7                  (_U_(0x1) << DEVEPT_EPEN7_Pos)

#define DEVEPT_EPEN8_Pos              8

#define DEVEPT_EPEN8                  (_U_(0x1) << DEVEPT_EPEN8_Pos)

#define DEVEPT_EPEN9_Pos              9

#define DEVEPT_EPEN9                  (_U_(0x1) << DEVEPT_EPEN9_Pos)

#define DEVEPT_EPRST0_Pos             16

#define DEVEPT_EPRST0                 (_U_(0x1) << DEVEPT_EPRST0_Pos)

#define DEVEPT_EPRST1_Pos             17

#define DEVEPT_EPRST1                 (_U_(0x1) << DEVEPT_EPRST1_Pos)

#define DEVEPT_EPRST2_Pos             18

#define DEVEPT_EPRST2                 (_U_(0x1) << DEVEPT_EPRST2_Pos)

#define DEVEPT_EPRST3_Pos             19

#define DEVEPT_EPRST3                 (_U_(0x1) << DEVEPT_EPRST3_Pos)

#define DEVEPT_EPRST4_Pos             20

#define DEVEPT_EPRST4                 (_U_(0x1) << DEVEPT_EPRST4_Pos)

#define DEVEPT_EPRST5_Pos             21

#define DEVEPT_EPRST5                 (_U_(0x1) << DEVEPT_EPRST5_Pos)

#define DEVEPT_EPRST6_Pos             22

#define DEVEPT_EPRST6                 (_U_(0x1) << DEVEPT_EPRST6_Pos)

#define DEVEPT_EPRST7_Pos             23

#define DEVEPT_EPRST7                 (_U_(0x1) << DEVEPT_EPRST7_Pos)

#define DEVEPT_EPRST8_Pos             24

#define DEVEPT_EPRST8                 (_U_(0x1) << DEVEPT_EPRST8_Pos)

#define DEVEPT_EPRST9_Pos             25

#define DEVEPT_EPRST9                 (_U_(0x1) << DEVEPT_EPRST9_Pos)

#define DEVEPT_Msk                    _U_(0x3FF03FF)

#define DEVEPT_EPEN_Pos               0

#define DEVEPT_EPEN                   (_U_(0x3FF) << DEVEPT_EPEN_Pos)

#define DEVEPT_EPRST_Pos              16

#define DEVEPT_EPRST                  (_U_(0x3FF) << DEVEPT_EPRST_Pos)

/* -------- DEVFNUM : (USBHS Offset: 0x20) (R/ 32) Device Frame Number Register -------- */


#define DEVFNUM_OFFSET                (0x20)

#define DEVFNUM_MFNUM_Pos             0

#define DEVFNUM_MFNUM                 (_U_(0x7) << DEVFNUM_MFNUM_Pos)

#define DEVFNUM_FNUM_Pos              3

#define DEVFNUM_FNUM                  (_U_(0x7FF) << DEVFNUM_FNUM_Pos)

#define DEVFNUM_FNCERR_Pos            15

#define DEVFNUM_FNCERR                (_U_(0x1) << DEVFNUM_FNCERR_Pos)

#define DEVFNUM_Msk                   _U_(0xBFFF)

/* -------- DEVEPTCFG : (USBHS Offset: 0x100) (R/W 32) Device Endpoint Configuration Register -------- */


#define DEVEPTCFG_OFFSET              (0x100)

#define DEVEPTCFG_ALLOC_Pos           1

#define DEVEPTCFG_ALLOC               (_U_(0x1) << DEVEPTCFG_ALLOC_Pos)

#define DEVEPTCFG_EPBK_Pos            2

#define DEVEPTCFG_EPBK                (_U_(0x3) << DEVEPTCFG_EPBK_Pos)

#define   DEVEPTCFG_EPBK_1_BANK_Val   _U_(0x0)

#define   DEVEPTCFG_EPBK_2_BANK_Val   _U_(0x1)

#define   DEVEPTCFG_EPBK_3_BANK_Val   _U_(0x2)

#define DEVEPTCFG_EPBK_1_BANK         (DEVEPTCFG_EPBK_1_BANK_Val << DEVEPTCFG_EPBK_Pos)

#define DEVEPTCFG_EPBK_2_BANK         (DEVEPTCFG_EPBK_2_BANK_Val << DEVEPTCFG_EPBK_Pos)

#define DEVEPTCFG_EPBK_3_BANK         (DEVEPTCFG_EPBK_3_BANK_Val << DEVEPTCFG_EPBK_Pos)

#define DEVEPTCFG_EPSIZE_Pos          4

#define DEVEPTCFG_EPSIZE              (_U_(0x7) << DEVEPTCFG_EPSIZE_Pos)

#define   DEVEPTCFG_EPSIZE_8_BYTE_Val _U_(0x0)

#define   DEVEPTCFG_EPSIZE_16_BYTE_Val _U_(0x1)

#define   DEVEPTCFG_EPSIZE_32_BYTE_Val _U_(0x2)

#define   DEVEPTCFG_EPSIZE_64_BYTE_Val _U_(0x3)

#define   DEVEPTCFG_EPSIZE_128_BYTE_Val _U_(0x4)

#define   DEVEPTCFG_EPSIZE_256_BYTE_Val _U_(0x5)

#define   DEVEPTCFG_EPSIZE_512_BYTE_Val _U_(0x6)

#define   DEVEPTCFG_EPSIZE_1024_BYTE_Val _U_(0x7)

#define DEVEPTCFG_EPSIZE_8_BYTE       (DEVEPTCFG_EPSIZE_8_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)

#define DEVEPTCFG_EPSIZE_16_BYTE      (DEVEPTCFG_EPSIZE_16_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)

#define DEVEPTCFG_EPSIZE_32_BYTE      (DEVEPTCFG_EPSIZE_32_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)

#define DEVEPTCFG_EPSIZE_64_BYTE      (DEVEPTCFG_EPSIZE_64_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)

#define DEVEPTCFG_EPSIZE_128_BYTE     (DEVEPTCFG_EPSIZE_128_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)

#define DEVEPTCFG_EPSIZE_256_BYTE     (DEVEPTCFG_EPSIZE_256_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)

#define DEVEPTCFG_EPSIZE_512_BYTE     (DEVEPTCFG_EPSIZE_512_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)

#define DEVEPTCFG_EPSIZE_1024_BYTE    (DEVEPTCFG_EPSIZE_1024_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)

#define DEVEPTCFG_EPDIR_Pos           8

#define DEVEPTCFG_EPDIR               (_U_(0x1) << DEVEPTCFG_EPDIR_Pos)

#define   DEVEPTCFG_EPDIR_OUT_Val     _U_(0x0)

#define   DEVEPTCFG_EPDIR_IN_Val      _U_(0x1)

#define DEVEPTCFG_EPDIR_OUT           (DEVEPTCFG_EPDIR_OUT_Val << DEVEPTCFG_EPDIR_Pos)

#define DEVEPTCFG_EPDIR_IN            (DEVEPTCFG_EPDIR_IN_Val << DEVEPTCFG_EPDIR_Pos)

#define DEVEPTCFG_AUTOSW_Pos          9

#define DEVEPTCFG_AUTOSW              (_U_(0x1) << DEVEPTCFG_AUTOSW_Pos)

#define DEVEPTCFG_EPTYPE_Pos          11

#define DEVEPTCFG_EPTYPE              (_U_(0x3) << DEVEPTCFG_EPTYPE_Pos)

#define   DEVEPTCFG_EPTYPE_CTRL_Val   _U_(0x0)

#define   DEVEPTCFG_EPTYPE_ISO_Val    _U_(0x1)

#define   DEVEPTCFG_EPTYPE_BLK_Val    _U_(0x2)

#define   DEVEPTCFG_EPTYPE_INTRPT_Val _U_(0x3)

#define DEVEPTCFG_EPTYPE_CTRL         (DEVEPTCFG_EPTYPE_CTRL_Val << DEVEPTCFG_EPTYPE_Pos)

#define DEVEPTCFG_EPTYPE_ISO          (DEVEPTCFG_EPTYPE_ISO_Val << DEVEPTCFG_EPTYPE_Pos)

#define DEVEPTCFG_EPTYPE_BLK          (DEVEPTCFG_EPTYPE_BLK_Val << DEVEPTCFG_EPTYPE_Pos)

#define DEVEPTCFG_EPTYPE_INTRPT       (DEVEPTCFG_EPTYPE_INTRPT_Val << DEVEPTCFG_EPTYPE_Pos)

#define DEVEPTCFG_NBTRANS_Pos         13

#define DEVEPTCFG_NBTRANS             (_U_(0x3) << DEVEPTCFG_NBTRANS_Pos)

#define   DEVEPTCFG_NBTRANS_0_TRANS_Val _U_(0x0)

#define   DEVEPTCFG_NBTRANS_1_TRANS_Val _U_(0x1)

#define   DEVEPTCFG_NBTRANS_2_TRANS_Val _U_(0x2)

#define   DEVEPTCFG_NBTRANS_3_TRANS_Val _U_(0x3)

#define DEVEPTCFG_NBTRANS_0_TRANS     (DEVEPTCFG_NBTRANS_0_TRANS_Val << DEVEPTCFG_NBTRANS_Pos)

#define DEVEPTCFG_NBTRANS_1_TRANS     (DEVEPTCFG_NBTRANS_1_TRANS_Val << DEVEPTCFG_NBTRANS_Pos)

#define DEVEPTCFG_NBTRANS_2_TRANS     (DEVEPTCFG_NBTRANS_2_TRANS_Val << DEVEPTCFG_NBTRANS_Pos)

#define DEVEPTCFG_NBTRANS_3_TRANS     (DEVEPTCFG_NBTRANS_3_TRANS_Val << DEVEPTCFG_NBTRANS_Pos)

#define DEVEPTCFG_Msk                 _U_(0x7B7E)

/* -------- DEVEPTISR : (USBHS Offset: 0x130) (R/ 32) Device Endpoint Interrupt Status Register -------- */


#define DEVEPTISR_OFFSET              (0x130)

#define DEVEPTISR_TXINI_Pos           0

#define DEVEPTISR_TXINI               (_U_(0x1) << DEVEPTISR_TXINI_Pos)

#define DEVEPTISR_RXOUTI_Pos          1

#define DEVEPTISR_RXOUTI              (_U_(0x1) << DEVEPTISR_RXOUTI_Pos)

#define DEVEPTISR_OVERFI_Pos          5

#define DEVEPTISR_OVERFI              (_U_(0x1) << DEVEPTISR_OVERFI_Pos)

#define DEVEPTISR_SHORTPACKET_Pos     7

#define DEVEPTISR_SHORTPACKET         (_U_(0x1) << DEVEPTISR_SHORTPACKET_Pos)

#define DEVEPTISR_DTSEQ_Pos           8

#define DEVEPTISR_DTSEQ               (_U_(0x3) << DEVEPTISR_DTSEQ_Pos)

#define   DEVEPTISR_DTSEQ_DATA0_Val   _U_(0x0)

#define   DEVEPTISR_DTSEQ_DATA1_Val   _U_(0x1)

#define   DEVEPTISR_DTSEQ_DATA2_Val   _U_(0x2)

#define   DEVEPTISR_DTSEQ_MDATA_Val   _U_(0x3)

#define DEVEPTISR_DTSEQ_DATA0         (DEVEPTISR_DTSEQ_DATA0_Val << DEVEPTISR_DTSEQ_Pos)

#define DEVEPTISR_DTSEQ_DATA1         (DEVEPTISR_DTSEQ_DATA1_Val << DEVEPTISR_DTSEQ_Pos)

#define DEVEPTISR_DTSEQ_DATA2         (DEVEPTISR_DTSEQ_DATA2_Val << DEVEPTISR_DTSEQ_Pos)

#define DEVEPTISR_DTSEQ_MDATA         (DEVEPTISR_DTSEQ_MDATA_Val << DEVEPTISR_DTSEQ_Pos)

#define DEVEPTISR_NBUSYBK_Pos         12

#define DEVEPTISR_NBUSYBK             (_U_(0x3) << DEVEPTISR_NBUSYBK_Pos)

#define   DEVEPTISR_NBUSYBK_0_BUSY_Val _U_(0x0)

#define   DEVEPTISR_NBUSYBK_1_BUSY_Val _U_(0x1)

#define   DEVEPTISR_NBUSYBK_2_BUSY_Val _U_(0x2)

#define   DEVEPTISR_NBUSYBK_3_BUSY_Val _U_(0x3)

#define DEVEPTISR_NBUSYBK_0_BUSY      (DEVEPTISR_NBUSYBK_0_BUSY_Val << DEVEPTISR_NBUSYBK_Pos)

#define DEVEPTISR_NBUSYBK_1_BUSY      (DEVEPTISR_NBUSYBK_1_BUSY_Val << DEVEPTISR_NBUSYBK_Pos)

#define DEVEPTISR_NBUSYBK_2_BUSY      (DEVEPTISR_NBUSYBK_2_BUSY_Val << DEVEPTISR_NBUSYBK_Pos)

#define DEVEPTISR_NBUSYBK_3_BUSY      (DEVEPTISR_NBUSYBK_3_BUSY_Val << DEVEPTISR_NBUSYBK_Pos)

#define DEVEPTISR_CURRBK_Pos          14

#define DEVEPTISR_CURRBK              (_U_(0x3) << DEVEPTISR_CURRBK_Pos)

#define   DEVEPTISR_CURRBK_BANK0_Val  _U_(0x0)

#define   DEVEPTISR_CURRBK_BANK1_Val  _U_(0x1)

#define   DEVEPTISR_CURRBK_BANK2_Val  _U_(0x2)

#define DEVEPTISR_CURRBK_BANK0        (DEVEPTISR_CURRBK_BANK0_Val << DEVEPTISR_CURRBK_Pos)

#define DEVEPTISR_CURRBK_BANK1        (DEVEPTISR_CURRBK_BANK1_Val << DEVEPTISR_CURRBK_Pos)

#define DEVEPTISR_CURRBK_BANK2        (DEVEPTISR_CURRBK_BANK2_Val << DEVEPTISR_CURRBK_Pos)

#define DEVEPTISR_RWALL_Pos           16

#define DEVEPTISR_RWALL               (_U_(0x1) << DEVEPTISR_RWALL_Pos)

#define DEVEPTISR_CFGOK_Pos           18

#define DEVEPTISR_CFGOK               (_U_(0x1) << DEVEPTISR_CFGOK_Pos)

#define DEVEPTISR_BYCT_Pos            20

#define DEVEPTISR_BYCT                (_U_(0x7FF) << DEVEPTISR_BYCT_Pos)

#define DEVEPTISR_Msk                 _U_(0x7FF5F3A3)

/* CTRL mode */

#define DEVEPTISR_CTRL_RXSTPI_Pos     2

#define DEVEPTISR_CTRL_RXSTPI         (_U_(0x1) << DEVEPTISR_CTRL_RXSTPI_Pos)

#define DEVEPTISR_CTRL_NAKOUTI_Pos    3

#define DEVEPTISR_CTRL_NAKOUTI        (_U_(0x1) << DEVEPTISR_CTRL_NAKOUTI_Pos)

#define DEVEPTISR_CTRL_NAKINI_Pos     4

#define DEVEPTISR_CTRL_NAKINI         (_U_(0x1) << DEVEPTISR_CTRL_NAKINI_Pos)

#define DEVEPTISR_CTRL_STALLEDI_Pos   6

#define DEVEPTISR_CTRL_STALLEDI       (_U_(0x1) << DEVEPTISR_CTRL_STALLEDI_Pos)

#define DEVEPTISR_CTRL_CTRLDIR_Pos    17

#define DEVEPTISR_CTRL_CTRLDIR        (_U_(0x1) << DEVEPTISR_CTRL_CTRLDIR_Pos)

#define DEVEPTISR_CTRL_Msk            _U_(0x2005C)

/* ISO mode */

#define DEVEPTISR_ISO_UNDERFI_Pos     2

#define DEVEPTISR_ISO_UNDERFI         (_U_(0x1) << DEVEPTISR_ISO_UNDERFI_Pos)

#define DEVEPTISR_ISO_HBISOINERRI_Pos 3

#define DEVEPTISR_ISO_HBISOINERRI     (_U_(0x1) << DEVEPTISR_ISO_HBISOINERRI_Pos)

#define DEVEPTISR_ISO_HBISOFLUSHI_Pos 4

#define DEVEPTISR_ISO_HBISOFLUSHI     (_U_(0x1) << DEVEPTISR_ISO_HBISOFLUSHI_Pos)

#define DEVEPTISR_ISO_CRCERRI_Pos     6

#define DEVEPTISR_ISO_CRCERRI         (_U_(0x1) << DEVEPTISR_ISO_CRCERRI_Pos)

#define DEVEPTISR_ISO_ERRORTRANS_Pos  10

#define DEVEPTISR_ISO_ERRORTRANS      (_U_(0x1) << DEVEPTISR_ISO_ERRORTRANS_Pos)

#define DEVEPTISR_ISO_Msk             _U_(0x45C)

/* BLK mode */

#define DEVEPTISR_BLK_RXSTPI_Pos      2

#define DEVEPTISR_BLK_RXSTPI          (_U_(0x1) << DEVEPTISR_BLK_RXSTPI_Pos)

#define DEVEPTISR_BLK_NAKOUTI_Pos     3

#define DEVEPTISR_BLK_NAKOUTI         (_U_(0x1) << DEVEPTISR_BLK_NAKOUTI_Pos)

#define DEVEPTISR_BLK_NAKINI_Pos      4

#define DEVEPTISR_BLK_NAKINI          (_U_(0x1) << DEVEPTISR_BLK_NAKINI_Pos)

#define DEVEPTISR_BLK_STALLEDI_Pos    6

#define DEVEPTISR_BLK_STALLEDI        (_U_(0x1) << DEVEPTISR_BLK_STALLEDI_Pos)

#define DEVEPTISR_BLK_CTRLDIR_Pos     17

#define DEVEPTISR_BLK_CTRLDIR         (_U_(0x1) << DEVEPTISR_BLK_CTRLDIR_Pos)

#define DEVEPTISR_BLK_Msk             _U_(0x2005C)

/* INTRPT mode */

#define DEVEPTISR_INTRPT_RXSTPI_Pos   2

#define DEVEPTISR_INTRPT_RXSTPI       (_U_(0x1) << DEVEPTISR_INTRPT_RXSTPI_Pos)

#define DEVEPTISR_INTRPT_NAKOUTI_Pos  3

#define DEVEPTISR_INTRPT_NAKOUTI      (_U_(0x1) << DEVEPTISR_INTRPT_NAKOUTI_Pos)

#define DEVEPTISR_INTRPT_NAKINI_Pos   4

#define DEVEPTISR_INTRPT_NAKINI       (_U_(0x1) << DEVEPTISR_INTRPT_NAKINI_Pos)

#define DEVEPTISR_INTRPT_STALLEDI_Pos 6

#define DEVEPTISR_INTRPT_STALLEDI     (_U_(0x1) << DEVEPTISR_INTRPT_STALLEDI_Pos)

#define DEVEPTISR_INTRPT_CTRLDIR_Pos  17

#define DEVEPTISR_INTRPT_CTRLDIR      (_U_(0x1) << DEVEPTISR_INTRPT_CTRLDIR_Pos)

#define DEVEPTISR_INTRPT_Msk          _U_(0x2005C)

/* -------- DEVEPTICR : (USBHS Offset: 0x160) (/W 32) Device Endpoint Interrupt Clear Register -------- */


#define DEVEPTICR_OFFSET              (0x160)

#define DEVEPTICR_TXINIC_Pos          0

#define DEVEPTICR_TXINIC              (_U_(0x1) << DEVEPTICR_TXINIC_Pos)

#define DEVEPTICR_RXOUTIC_Pos         1

#define DEVEPTICR_RXOUTIC             (_U_(0x1) << DEVEPTICR_RXOUTIC_Pos)

#define DEVEPTICR_OVERFIC_Pos         5

#define DEVEPTICR_OVERFIC             (_U_(0x1) << DEVEPTICR_OVERFIC_Pos)

#define DEVEPTICR_SHORTPACKETC_Pos    7

#define DEVEPTICR_SHORTPACKETC        (_U_(0x1) << DEVEPTICR_SHORTPACKETC_Pos)

#define DEVEPTICR_Msk                 _U_(0xA3)

/* CTRL mode */

#define DEVEPTICR_CTRL_RXSTPIC_Pos    2

#define DEVEPTICR_CTRL_RXSTPIC        (_U_(0x1) << DEVEPTICR_CTRL_RXSTPIC_Pos)

#define DEVEPTICR_CTRL_NAKOUTIC_Pos   3

#define DEVEPTICR_CTRL_NAKOUTIC       (_U_(0x1) << DEVEPTICR_CTRL_NAKOUTIC_Pos)

#define DEVEPTICR_CTRL_NAKINIC_Pos    4

#define DEVEPTICR_CTRL_NAKINIC        (_U_(0x1) << DEVEPTICR_CTRL_NAKINIC_Pos)

#define DEVEPTICR_CTRL_STALLEDIC_Pos  6

#define DEVEPTICR_CTRL_STALLEDIC      (_U_(0x1) << DEVEPTICR_CTRL_STALLEDIC_Pos)

#define DEVEPTICR_CTRL_Msk            _U_(0x5C)

/* ISO mode */

#define DEVEPTICR_ISO_UNDERFIC_Pos    2

#define DEVEPTICR_ISO_UNDERFIC        (_U_(0x1) << DEVEPTICR_ISO_UNDERFIC_Pos)

#define DEVEPTICR_ISO_HBISOINERRIC_Pos 3

#define DEVEPTICR_ISO_HBISOINERRIC     (_U_(0x1) << DEVEPTICR_ISO_HBISOINERRIC_Pos)

#define DEVEPTICR_ISO_HBISOFLUSHIC_Pos 4

#define DEVEPTICR_ISO_HBISOFLUSHIC     (_U_(0x1) << DEVEPTICR_ISO_HBISOFLUSHIC_Pos)

#define DEVEPTICR_ISO_CRCERRIC_Pos    6

#define DEVEPTICR_ISO_CRCERRIC        (_U_(0x1) << DEVEPTICR_ISO_CRCERRIC_Pos)

#define DEVEPTICR_ISO_Msk             _U_(0x5C)

/* BLK mode */

#define DEVEPTICR_BLK_RXSTPIC_Pos     2

#define DEVEPTICR_BLK_RXSTPIC         (_U_(0x1) << DEVEPTICR_BLK_RXSTPIC_Pos)

#define DEVEPTICR_BLK_NAKOUTIC_Pos    3

#define DEVEPTICR_BLK_NAKOUTIC        (_U_(0x1) << DEVEPTICR_BLK_NAKOUTIC_Pos)

#define DEVEPTICR_BLK_NAKINIC_Pos     4

#define DEVEPTICR_BLK_NAKINIC         (_U_(0x1) << DEVEPTICR_BLK_NAKINIC_Pos)

#define DEVEPTICR_BLK_STALLEDIC_Pos   6

#define DEVEPTICR_BLK_STALLEDIC       (_U_(0x1) << DEVEPTICR_BLK_STALLEDIC_Pos)

#define DEVEPTICR_BLK_Msk             _U_(0x5C)

/* INTRPT mode */

#define DEVEPTICR_INTRPT_RXSTPIC_Pos  2

#define DEVEPTICR_INTRPT_RXSTPIC      (_U_(0x1) << DEVEPTICR_INTRPT_RXSTPIC_Pos)

#define DEVEPTICR_INTRPT_NAKOUTIC_Pos 3

#define DEVEPTICR_INTRPT_NAKOUTIC     (_U_(0x1) << DEVEPTICR_INTRPT_NAKOUTIC_Pos)

#define DEVEPTICR_INTRPT_NAKINIC_Pos  4

#define DEVEPTICR_INTRPT_NAKINIC      (_U_(0x1) << DEVEPTICR_INTRPT_NAKINIC_Pos)

#define DEVEPTICR_INTRPT_STALLEDIC_Pos 6

#define DEVEPTICR_INTRPT_STALLEDIC     (_U_(0x1) << DEVEPTICR_INTRPT_STALLEDIC_Pos)

#define DEVEPTICR_INTRPT_Msk          _U_(0x5C)

/* -------- DEVEPTIFR : (USBHS Offset: 0x190) (/W 32) Device Endpoint Interrupt Set Register -------- */


#define DEVEPTIFR_OFFSET              (0x190)

#define DEVEPTIFR_TXINIS_Pos          0

#define DEVEPTIFR_TXINIS              (_U_(0x1) << DEVEPTIFR_TXINIS_Pos)

#define DEVEPTIFR_RXOUTIS_Pos         1

#define DEVEPTIFR_RXOUTIS             (_U_(0x1) << DEVEPTIFR_RXOUTIS_Pos)

#define DEVEPTIFR_OVERFIS_Pos         5

#define DEVEPTIFR_OVERFIS             (_U_(0x1) << DEVEPTIFR_OVERFIS_Pos)

#define DEVEPTIFR_SHORTPACKETS_Pos    7

#define DEVEPTIFR_SHORTPACKETS        (_U_(0x1) << DEVEPTIFR_SHORTPACKETS_Pos)

#define DEVEPTIFR_NBUSYBKS_Pos        12

#define DEVEPTIFR_NBUSYBKS            (_U_(0x1) << DEVEPTIFR_NBUSYBKS_Pos)

#define DEVEPTIFR_Msk                 _U_(0x10A3)

/* CTRL mode */

#define DEVEPTIFR_CTRL_RXSTPIS_Pos    2

#define DEVEPTIFR_CTRL_RXSTPIS        (_U_(0x1) << DEVEPTIFR_CTRL_RXSTPIS_Pos)

#define DEVEPTIFR_CTRL_NAKOUTIS_Pos   3

#define DEVEPTIFR_CTRL_NAKOUTIS       (_U_(0x1) << DEVEPTIFR_CTRL_NAKOUTIS_Pos)

#define DEVEPTIFR_CTRL_NAKINIS_Pos    4

#define DEVEPTIFR_CTRL_NAKINIS        (_U_(0x1) << DEVEPTIFR_CTRL_NAKINIS_Pos)

#define DEVEPTIFR_CTRL_STALLEDIS_Pos  6

#define DEVEPTIFR_CTRL_STALLEDIS      (_U_(0x1) << DEVEPTIFR_CTRL_STALLEDIS_Pos)

#define DEVEPTIFR_CTRL_Msk            _U_(0x5C)

/* ISO mode */

#define DEVEPTIFR_ISO_UNDERFIS_Pos    2

#define DEVEPTIFR_ISO_UNDERFIS        (_U_(0x1) << DEVEPTIFR_ISO_UNDERFIS_Pos)

#define DEVEPTIFR_ISO_HBISOINERRIS_Pos 3

#define DEVEPTIFR_ISO_HBISOINERRIS     (_U_(0x1) << DEVEPTIFR_ISO_HBISOINERRIS_Pos)

#define DEVEPTIFR_ISO_HBISOFLUSHIS_Pos 4

#define DEVEPTIFR_ISO_HBISOFLUSHIS     (_U_(0x1) << DEVEPTIFR_ISO_HBISOFLUSHIS_Pos)

#define DEVEPTIFR_ISO_CRCERRIS_Pos    6

#define DEVEPTIFR_ISO_CRCERRIS        (_U_(0x1) << DEVEPTIFR_ISO_CRCERRIS_Pos)

#define DEVEPTIFR_ISO_Msk             _U_(0x5C)

/* BLK mode */

#define DEVEPTIFR_BLK_RXSTPIS_Pos     2

#define DEVEPTIFR_BLK_RXSTPIS         (_U_(0x1) << DEVEPTIFR_BLK_RXSTPIS_Pos)

#define DEVEPTIFR_BLK_NAKOUTIS_Pos    3

#define DEVEPTIFR_BLK_NAKOUTIS        (_U_(0x1) << DEVEPTIFR_BLK_NAKOUTIS_Pos)

#define DEVEPTIFR_BLK_NAKINIS_Pos     4

#define DEVEPTIFR_BLK_NAKINIS         (_U_(0x1) << DEVEPTIFR_BLK_NAKINIS_Pos)

#define DEVEPTIFR_BLK_STALLEDIS_Pos   6

#define DEVEPTIFR_BLK_STALLEDIS       (_U_(0x1) << DEVEPTIFR_BLK_STALLEDIS_Pos)

#define DEVEPTIFR_BLK_Msk             _U_(0x5C)

/* INTRPT mode */

#define DEVEPTIFR_INTRPT_RXSTPIS_Pos  2

#define DEVEPTIFR_INTRPT_RXSTPIS      (_U_(0x1) << DEVEPTIFR_INTRPT_RXSTPIS_Pos)

#define DEVEPTIFR_INTRPT_NAKOUTIS_Pos 3

#define DEVEPTIFR_INTRPT_NAKOUTIS     (_U_(0x1) << DEVEPTIFR_INTRPT_NAKOUTIS_Pos)

#define DEVEPTIFR_INTRPT_NAKINIS_Pos  4

#define DEVEPTIFR_INTRPT_NAKINIS      (_U_(0x1) << DEVEPTIFR_INTRPT_NAKINIS_Pos)

#define DEVEPTIFR_INTRPT_STALLEDIS_Pos 6

#define DEVEPTIFR_INTRPT_STALLEDIS     (_U_(0x1) << DEVEPTIFR_INTRPT_STALLEDIS_Pos)

#define DEVEPTIFR_INTRPT_Msk          _U_(0x5C)

/* -------- DEVEPTIMR : (USBHS Offset: 0x1c0) (R/ 32) Device Endpoint Interrupt Mask Register -------- */


#define DEVEPTIMR_OFFSET              (0x1C0)

#define DEVEPTIMR_TXINE_Pos           0

#define DEVEPTIMR_TXINE               (_U_(0x1) << DEVEPTIMR_TXINE_Pos)

#define DEVEPTIMR_RXOUTE_Pos          1

#define DEVEPTIMR_RXOUTE              (_U_(0x1) << DEVEPTIMR_RXOUTE_Pos)

#define DEVEPTIMR_OVERFE_Pos          5

#define DEVEPTIMR_OVERFE              (_U_(0x1) << DEVEPTIMR_OVERFE_Pos)

#define DEVEPTIMR_SHORTPACKETE_Pos    7

#define DEVEPTIMR_SHORTPACKETE        (_U_(0x1) << DEVEPTIMR_SHORTPACKETE_Pos)

#define DEVEPTIMR_NBUSYBKE_Pos        12

#define DEVEPTIMR_NBUSYBKE            (_U_(0x1) << DEVEPTIMR_NBUSYBKE_Pos)

#define DEVEPTIMR_KILLBK_Pos          13

#define DEVEPTIMR_KILLBK              (_U_(0x1) << DEVEPTIMR_KILLBK_Pos)

#define DEVEPTIMR_FIFOCON_Pos         14

#define DEVEPTIMR_FIFOCON             (_U_(0x1) << DEVEPTIMR_FIFOCON_Pos)

#define DEVEPTIMR_EPDISHDMA_Pos       16

#define DEVEPTIMR_EPDISHDMA           (_U_(0x1) << DEVEPTIMR_EPDISHDMA_Pos)

#define DEVEPTIMR_RSTDT_Pos           18

#define DEVEPTIMR_RSTDT               (_U_(0x1) << DEVEPTIMR_RSTDT_Pos)

#define DEVEPTIMR_Msk                 _U_(0x570A3)

/* CTRL mode */

#define DEVEPTIMR_CTRL_RXSTPE_Pos     2

#define DEVEPTIMR_CTRL_RXSTPE         (_U_(0x1) << DEVEPTIMR_CTRL_RXSTPE_Pos)

#define DEVEPTIMR_CTRL_NAKOUTE_Pos    3

#define DEVEPTIMR_CTRL_NAKOUTE        (_U_(0x1) << DEVEPTIMR_CTRL_NAKOUTE_Pos)

#define DEVEPTIMR_CTRL_NAKINE_Pos     4

#define DEVEPTIMR_CTRL_NAKINE         (_U_(0x1) << DEVEPTIMR_CTRL_NAKINE_Pos)

#define DEVEPTIMR_CTRL_STALLEDE_Pos   6

#define DEVEPTIMR_CTRL_STALLEDE       (_U_(0x1) << DEVEPTIMR_CTRL_STALLEDE_Pos)

#define DEVEPTIMR_CTRL_NYETDIS_Pos    17

#define DEVEPTIMR_CTRL_NYETDIS        (_U_(0x1) << DEVEPTIMR_CTRL_NYETDIS_Pos)

#define DEVEPTIMR_CTRL_STALLRQ_Pos    19

#define DEVEPTIMR_CTRL_STALLRQ        (_U_(0x1) << DEVEPTIMR_CTRL_STALLRQ_Pos)

#define DEVEPTIMR_CTRL_Msk            _U_(0xA005C)

/* ISO mode */

#define DEVEPTIMR_ISO_UNDERFE_Pos     2

#define DEVEPTIMR_ISO_UNDERFE         (_U_(0x1) << DEVEPTIMR_ISO_UNDERFE_Pos)

#define DEVEPTIMR_ISO_HBISOINERRE_Pos 3

#define DEVEPTIMR_ISO_HBISOINERRE     (_U_(0x1) << DEVEPTIMR_ISO_HBISOINERRE_Pos)

#define DEVEPTIMR_ISO_HBISOFLUSHE_Pos 4

#define DEVEPTIMR_ISO_HBISOFLUSHE     (_U_(0x1) << DEVEPTIMR_ISO_HBISOFLUSHE_Pos)

#define DEVEPTIMR_ISO_CRCERRE_Pos     6

#define DEVEPTIMR_ISO_CRCERRE         (_U_(0x1) << DEVEPTIMR_ISO_CRCERRE_Pos)

#define DEVEPTIMR_ISO_MDATAE_Pos      8

#define DEVEPTIMR_ISO_MDATAE          (_U_(0x1) << DEVEPTIMR_ISO_MDATAE_Pos)

#define DEVEPTIMR_ISO_DATAXE_Pos      9

#define DEVEPTIMR_ISO_DATAXE          (_U_(0x1) << DEVEPTIMR_ISO_DATAXE_Pos)

#define DEVEPTIMR_ISO_ERRORTRANSE_Pos 10

#define DEVEPTIMR_ISO_ERRORTRANSE     (_U_(0x1) << DEVEPTIMR_ISO_ERRORTRANSE_Pos)

#define DEVEPTIMR_ISO_Msk             _U_(0x75C)

/* BLK mode */

#define DEVEPTIMR_BLK_RXSTPE_Pos      2

#define DEVEPTIMR_BLK_RXSTPE          (_U_(0x1) << DEVEPTIMR_BLK_RXSTPE_Pos)

#define DEVEPTIMR_BLK_NAKOUTE_Pos     3

#define DEVEPTIMR_BLK_NAKOUTE         (_U_(0x1) << DEVEPTIMR_BLK_NAKOUTE_Pos)

#define DEVEPTIMR_BLK_NAKINE_Pos      4

#define DEVEPTIMR_BLK_NAKINE          (_U_(0x1) << DEVEPTIMR_BLK_NAKINE_Pos)

#define DEVEPTIMR_BLK_STALLEDE_Pos    6

#define DEVEPTIMR_BLK_STALLEDE        (_U_(0x1) << DEVEPTIMR_BLK_STALLEDE_Pos)

#define DEVEPTIMR_BLK_NYETDIS_Pos     17

#define DEVEPTIMR_BLK_NYETDIS         (_U_(0x1) << DEVEPTIMR_BLK_NYETDIS_Pos)

#define DEVEPTIMR_BLK_STALLRQ_Pos     19

#define DEVEPTIMR_BLK_STALLRQ         (_U_(0x1) << DEVEPTIMR_BLK_STALLRQ_Pos)

#define DEVEPTIMR_BLK_Msk             _U_(0xA005C)

/* INTRPT mode */

#define DEVEPTIMR_INTRPT_RXSTPE_Pos   2

#define DEVEPTIMR_INTRPT_RXSTPE       (_U_(0x1) << DEVEPTIMR_INTRPT_RXSTPE_Pos)

#define DEVEPTIMR_INTRPT_NAKOUTE_Pos  3

#define DEVEPTIMR_INTRPT_NAKOUTE      (_U_(0x1) << DEVEPTIMR_INTRPT_NAKOUTE_Pos)

#define DEVEPTIMR_INTRPT_NAKINE_Pos   4

#define DEVEPTIMR_INTRPT_NAKINE       (_U_(0x1) << DEVEPTIMR_INTRPT_NAKINE_Pos)

#define DEVEPTIMR_INTRPT_STALLEDE_Pos 6

#define DEVEPTIMR_INTRPT_STALLEDE     (_U_(0x1) << DEVEPTIMR_INTRPT_STALLEDE_Pos)

#define DEVEPTIMR_INTRPT_NYETDIS_Pos  17

#define DEVEPTIMR_INTRPT_NYETDIS      (_U_(0x1) << DEVEPTIMR_INTRPT_NYETDIS_Pos)

#define DEVEPTIMR_INTRPT_STALLRQ_Pos  19

#define DEVEPTIMR_INTRPT_STALLRQ      (_U_(0x1) << DEVEPTIMR_INTRPT_STALLRQ_Pos)

#define DEVEPTIMR_INTRPT_Msk          _U_(0xA005C)

/* -------- DEVEPTIER : (USBHS Offset: 0x1f0) (/W 32) Device Endpoint Interrupt Enable Register -------- */


#define DEVEPTIER_OFFSET              (0x1F0)

#define DEVEPTIER_TXINES_Pos          0

#define DEVEPTIER_TXINES              (_U_(0x1) << DEVEPTIER_TXINES_Pos)

#define DEVEPTIER_RXOUTES_Pos         1

#define DEVEPTIER_RXOUTES             (_U_(0x1) << DEVEPTIER_RXOUTES_Pos)

#define DEVEPTIER_OVERFES_Pos         5

#define DEVEPTIER_OVERFES             (_U_(0x1) << DEVEPTIER_OVERFES_Pos)

#define DEVEPTIER_SHORTPACKETES_Pos   7

#define DEVEPTIER_SHORTPACKETES       (_U_(0x1) << DEVEPTIER_SHORTPACKETES_Pos)

#define DEVEPTIER_NBUSYBKES_Pos       12

#define DEVEPTIER_NBUSYBKES           (_U_(0x1) << DEVEPTIER_NBUSYBKES_Pos)

#define DEVEPTIER_KILLBKS_Pos         13

#define DEVEPTIER_KILLBKS             (_U_(0x1) << DEVEPTIER_KILLBKS_Pos)

#define DEVEPTIER_FIFOCONS_Pos        14

#define DEVEPTIER_FIFOCONS            (_U_(0x1) << DEVEPTIER_FIFOCONS_Pos)

#define DEVEPTIER_EPDISHDMAS_Pos      16

#define DEVEPTIER_EPDISHDMAS          (_U_(0x1) << DEVEPTIER_EPDISHDMAS_Pos)

#define DEVEPTIER_RSTDTS_Pos          18

#define DEVEPTIER_RSTDTS              (_U_(0x1) << DEVEPTIER_RSTDTS_Pos)

#define DEVEPTIER_Msk                 _U_(0x570A3)

/* CTRL mode */

#define DEVEPTIER_CTRL_RXSTPES_Pos    2

#define DEVEPTIER_CTRL_RXSTPES        (_U_(0x1) << DEVEPTIER_CTRL_RXSTPES_Pos)

#define DEVEPTIER_CTRL_NAKOUTES_Pos   3

#define DEVEPTIER_CTRL_NAKOUTES       (_U_(0x1) << DEVEPTIER_CTRL_NAKOUTES_Pos)

#define DEVEPTIER_CTRL_NAKINES_Pos    4

#define DEVEPTIER_CTRL_NAKINES        (_U_(0x1) << DEVEPTIER_CTRL_NAKINES_Pos)

#define DEVEPTIER_CTRL_STALLEDES_Pos  6

#define DEVEPTIER_CTRL_STALLEDES      (_U_(0x1) << DEVEPTIER_CTRL_STALLEDES_Pos)

#define DEVEPTIER_CTRL_NYETDISS_Pos   17

#define DEVEPTIER_CTRL_NYETDISS       (_U_(0x1) << DEVEPTIER_CTRL_NYETDISS_Pos)

#define DEVEPTIER_CTRL_STALLRQS_Pos   19

#define DEVEPTIER_CTRL_STALLRQS       (_U_(0x1) << DEVEPTIER_CTRL_STALLRQS_Pos)

#define DEVEPTIER_CTRL_Msk            _U_(0xA005C)

/* ISO mode */

#define DEVEPTIER_ISO_UNDERFES_Pos    2

#define DEVEPTIER_ISO_UNDERFES        (_U_(0x1) << DEVEPTIER_ISO_UNDERFES_Pos)

#define DEVEPTIER_ISO_HBISOINERRES_Pos 3

#define DEVEPTIER_ISO_HBISOINERRES     (_U_(0x1) << DEVEPTIER_ISO_HBISOINERRES_Pos)

#define DEVEPTIER_ISO_HBISOFLUSHES_Pos 4

#define DEVEPTIER_ISO_HBISOFLUSHES     (_U_(0x1) << DEVEPTIER_ISO_HBISOFLUSHES_Pos)

#define DEVEPTIER_ISO_CRCERRES_Pos    6

#define DEVEPTIER_ISO_CRCERRES        (_U_(0x1) << DEVEPTIER_ISO_CRCERRES_Pos)

#define DEVEPTIER_ISO_MDATAES_Pos     8

#define DEVEPTIER_ISO_MDATAES         (_U_(0x1) << DEVEPTIER_ISO_MDATAES_Pos)

#define DEVEPTIER_ISO_DATAXES_Pos     9

#define DEVEPTIER_ISO_DATAXES         (_U_(0x1) << DEVEPTIER_ISO_DATAXES_Pos)

#define DEVEPTIER_ISO_ERRORTRANSES_Pos 10

#define DEVEPTIER_ISO_ERRORTRANSES     (_U_(0x1) << DEVEPTIER_ISO_ERRORTRANSES_Pos)

#define DEVEPTIER_ISO_Msk             _U_(0x75C)

/* BLK mode */

#define DEVEPTIER_BLK_RXSTPES_Pos     2

#define DEVEPTIER_BLK_RXSTPES         (_U_(0x1) << DEVEPTIER_BLK_RXSTPES_Pos)

#define DEVEPTIER_BLK_NAKOUTES_Pos    3

#define DEVEPTIER_BLK_NAKOUTES        (_U_(0x1) << DEVEPTIER_BLK_NAKOUTES_Pos)

#define DEVEPTIER_BLK_NAKINES_Pos     4

#define DEVEPTIER_BLK_NAKINES         (_U_(0x1) << DEVEPTIER_BLK_NAKINES_Pos)

#define DEVEPTIER_BLK_STALLEDES_Pos   6

#define DEVEPTIER_BLK_STALLEDES       (_U_(0x1) << DEVEPTIER_BLK_STALLEDES_Pos)

#define DEVEPTIER_BLK_NYETDISS_Pos    17

#define DEVEPTIER_BLK_NYETDISS        (_U_(0x1) << DEVEPTIER_BLK_NYETDISS_Pos)

#define DEVEPTIER_BLK_STALLRQS_Pos    19

#define DEVEPTIER_BLK_STALLRQS        (_U_(0x1) << DEVEPTIER_BLK_STALLRQS_Pos)

#define DEVEPTIER_BLK_Msk             _U_(0xA005C)

/* INTRPT mode */

#define DEVEPTIER_INTRPT_RXSTPES_Pos  2

#define DEVEPTIER_INTRPT_RXSTPES      (_U_(0x1) << DEVEPTIER_INTRPT_RXSTPES_Pos)

#define DEVEPTIER_INTRPT_NAKOUTES_Pos 3

#define DEVEPTIER_INTRPT_NAKOUTES     (_U_(0x1) << DEVEPTIER_INTRPT_NAKOUTES_Pos)

#define DEVEPTIER_INTRPT_NAKINES_Pos  4

#define DEVEPTIER_INTRPT_NAKINES      (_U_(0x1) << DEVEPTIER_INTRPT_NAKINES_Pos)

#define DEVEPTIER_INTRPT_STALLEDES_Pos 6

#define DEVEPTIER_INTRPT_STALLEDES     (_U_(0x1) << DEVEPTIER_INTRPT_STALLEDES_Pos)

#define DEVEPTIER_INTRPT_NYETDISS_Pos 17

#define DEVEPTIER_INTRPT_NYETDISS     (_U_(0x1) << DEVEPTIER_INTRPT_NYETDISS_Pos)

#define DEVEPTIER_INTRPT_STALLRQS_Pos 19

#define DEVEPTIER_INTRPT_STALLRQS     (_U_(0x1) << DEVEPTIER_INTRPT_STALLRQS_Pos)

#define DEVEPTIER_INTRPT_Msk          _U_(0xA005C)

/* -------- DEVEPTIDR : (USBHS Offset: 0x220) (/W 32) Device Endpoint Interrupt Disable Register -------- */


#define DEVEPTIDR_OFFSET              (0x220)

#define DEVEPTIDR_TXINEC_Pos          0

#define DEVEPTIDR_TXINEC              (_U_(0x1) << DEVEPTIDR_TXINEC_Pos)

#define DEVEPTIDR_RXOUTEC_Pos         1

#define DEVEPTIDR_RXOUTEC             (_U_(0x1) << DEVEPTIDR_RXOUTEC_Pos)

#define DEVEPTIDR_OVERFEC_Pos         5

#define DEVEPTIDR_OVERFEC             (_U_(0x1) << DEVEPTIDR_OVERFEC_Pos)

#define DEVEPTIDR_SHORTPACKETEC_Pos   7

#define DEVEPTIDR_SHORTPACKETEC       (_U_(0x1) << DEVEPTIDR_SHORTPACKETEC_Pos)

#define DEVEPTIDR_NBUSYBKEC_Pos       12

#define DEVEPTIDR_NBUSYBKEC           (_U_(0x1) << DEVEPTIDR_NBUSYBKEC_Pos)

#define DEVEPTIDR_FIFOCONC_Pos        14

#define DEVEPTIDR_FIFOCONC            (_U_(0x1) << DEVEPTIDR_FIFOCONC_Pos)

#define DEVEPTIDR_EPDISHDMAC_Pos      16

#define DEVEPTIDR_EPDISHDMAC          (_U_(0x1) << DEVEPTIDR_EPDISHDMAC_Pos)

#define DEVEPTIDR_Msk                 _U_(0x150A3)

/* CTRL mode */

#define DEVEPTIDR_CTRL_RXSTPEC_Pos    2

#define DEVEPTIDR_CTRL_RXSTPEC        (_U_(0x1) << DEVEPTIDR_CTRL_RXSTPEC_Pos)

#define DEVEPTIDR_CTRL_NAKOUTEC_Pos   3

#define DEVEPTIDR_CTRL_NAKOUTEC       (_U_(0x1) << DEVEPTIDR_CTRL_NAKOUTEC_Pos)

#define DEVEPTIDR_CTRL_NAKINEC_Pos    4

#define DEVEPTIDR_CTRL_NAKINEC        (_U_(0x1) << DEVEPTIDR_CTRL_NAKINEC_Pos)

#define DEVEPTIDR_CTRL_STALLEDEC_Pos  6

#define DEVEPTIDR_CTRL_STALLEDEC      (_U_(0x1) << DEVEPTIDR_CTRL_STALLEDEC_Pos)

#define DEVEPTIDR_CTRL_NYETDISC_Pos   17

#define DEVEPTIDR_CTRL_NYETDISC       (_U_(0x1) << DEVEPTIDR_CTRL_NYETDISC_Pos)

#define DEVEPTIDR_CTRL_STALLRQC_Pos   19

#define DEVEPTIDR_CTRL_STALLRQC       (_U_(0x1) << DEVEPTIDR_CTRL_STALLRQC_Pos)

#define DEVEPTIDR_CTRL_Msk            _U_(0xA005C)

/* ISO mode */

#define DEVEPTIDR_ISO_UNDERFEC_Pos    2

#define DEVEPTIDR_ISO_UNDERFEC        (_U_(0x1) << DEVEPTIDR_ISO_UNDERFEC_Pos)

#define DEVEPTIDR_ISO_HBISOINERREC_Pos 3

#define DEVEPTIDR_ISO_HBISOINERREC     (_U_(0x1) << DEVEPTIDR_ISO_HBISOINERREC_Pos)

#define DEVEPTIDR_ISO_HBISOFLUSHEC_Pos 4

#define DEVEPTIDR_ISO_HBISOFLUSHEC     (_U_(0x1) << DEVEPTIDR_ISO_HBISOFLUSHEC_Pos)

#define DEVEPTIDR_ISO_MDATAEC_Pos     8

#define DEVEPTIDR_ISO_MDATAEC         (_U_(0x1) << DEVEPTIDR_ISO_MDATAEC_Pos)

#define DEVEPTIDR_ISO_DATAXEC_Pos     9

#define DEVEPTIDR_ISO_DATAXEC         (_U_(0x1) << DEVEPTIDR_ISO_DATAXEC_Pos)

#define DEVEPTIDR_ISO_ERRORTRANSEC_Pos 10

#define DEVEPTIDR_ISO_ERRORTRANSEC     (_U_(0x1) << DEVEPTIDR_ISO_ERRORTRANSEC_Pos)

#define DEVEPTIDR_ISO_Msk             _U_(0x71C)

/* BLK mode */

#define DEVEPTIDR_BLK_RXSTPEC_Pos     2

#define DEVEPTIDR_BLK_RXSTPEC         (_U_(0x1) << DEVEPTIDR_BLK_RXSTPEC_Pos)

#define DEVEPTIDR_BLK_NAKOUTEC_Pos    3

#define DEVEPTIDR_BLK_NAKOUTEC        (_U_(0x1) << DEVEPTIDR_BLK_NAKOUTEC_Pos)

#define DEVEPTIDR_BLK_NAKINEC_Pos     4

#define DEVEPTIDR_BLK_NAKINEC         (_U_(0x1) << DEVEPTIDR_BLK_NAKINEC_Pos)

#define DEVEPTIDR_BLK_STALLEDEC_Pos   6

#define DEVEPTIDR_BLK_STALLEDEC       (_U_(0x1) << DEVEPTIDR_BLK_STALLEDEC_Pos)

#define DEVEPTIDR_BLK_NYETDISC_Pos    17

#define DEVEPTIDR_BLK_NYETDISC        (_U_(0x1) << DEVEPTIDR_BLK_NYETDISC_Pos)

#define DEVEPTIDR_BLK_STALLRQC_Pos    19

#define DEVEPTIDR_BLK_STALLRQC        (_U_(0x1) << DEVEPTIDR_BLK_STALLRQC_Pos)

#define DEVEPTIDR_BLK_Msk             _U_(0xA005C)

/* INTRPT mode */

#define DEVEPTIDR_INTRPT_RXSTPEC_Pos  2

#define DEVEPTIDR_INTRPT_RXSTPEC      (_U_(0x1) << DEVEPTIDR_INTRPT_RXSTPEC_Pos)

#define DEVEPTIDR_INTRPT_NAKOUTEC_Pos 3

#define DEVEPTIDR_INTRPT_NAKOUTEC     (_U_(0x1) << DEVEPTIDR_INTRPT_NAKOUTEC_Pos)

#define DEVEPTIDR_INTRPT_NAKINEC_Pos  4

#define DEVEPTIDR_INTRPT_NAKINEC      (_U_(0x1) << DEVEPTIDR_INTRPT_NAKINEC_Pos)

#define DEVEPTIDR_INTRPT_STALLEDEC_Pos 6

#define DEVEPTIDR_INTRPT_STALLEDEC     (_U_(0x1) << DEVEPTIDR_INTRPT_STALLEDEC_Pos)

#define DEVEPTIDR_INTRPT_NYETDISC_Pos 17

#define DEVEPTIDR_INTRPT_NYETDISC     (_U_(0x1) << DEVEPTIDR_INTRPT_NYETDISC_Pos)

#define DEVEPTIDR_INTRPT_STALLRQC_Pos 19

#define DEVEPTIDR_INTRPT_STALLRQC     (_U_(0x1) << DEVEPTIDR_INTRPT_STALLRQC_Pos)

#define DEVEPTIDR_INTRPT_Msk          _U_(0xA005C)

/* -------- HSTCTRL : (USBHS Offset: 0x400) (R/W 32) Host General Control Register -------- */


#define HSTCTRL_OFFSET                (0x400)

#define HSTCTRL_SOFE_Pos              8

#define HSTCTRL_SOFE                  (_U_(0x1) << HSTCTRL_SOFE_Pos)

#define HSTCTRL_RESET_Pos             9

#define HSTCTRL_RESET                 (_U_(0x1) << HSTCTRL_RESET_Pos)

#define HSTCTRL_RESUME_Pos            10

#define HSTCTRL_RESUME                (_U_(0x1) << HSTCTRL_RESUME_Pos)

#define HSTCTRL_SPDCONF_Pos           12

#define HSTCTRL_SPDCONF               (_U_(0x3) << HSTCTRL_SPDCONF_Pos)

#define   HSTCTRL_SPDCONF_NORMAL_Val  _U_(0x0)

#define   HSTCTRL_SPDCONF_LOW_POWER_Val _U_(0x1)

#define   HSTCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2)

#define   HSTCTRL_SPDCONF_FORCED_FS_Val _U_(0x3)

#define HSTCTRL_SPDCONF_NORMAL        (HSTCTRL_SPDCONF_NORMAL_Val << HSTCTRL_SPDCONF_Pos)

#define HSTCTRL_SPDCONF_LOW_POWER     (HSTCTRL_SPDCONF_LOW_POWER_Val << HSTCTRL_SPDCONF_Pos)

#define HSTCTRL_SPDCONF_HIGH_SPEED    (HSTCTRL_SPDCONF_HIGH_SPEED_Val << HSTCTRL_SPDCONF_Pos)

#define HSTCTRL_SPDCONF_FORCED_FS     (HSTCTRL_SPDCONF_FORCED_FS_Val << HSTCTRL_SPDCONF_Pos)

#define HSTCTRL_Msk                   _U_(0x3700)

/* -------- HSTISR : (USBHS Offset: 0x404) (R/ 32) Host Global Interrupt Status Register -------- */


#define HSTISR_OFFSET                 (0x404)

#define HSTISR_DCONNI_Pos             0

#define HSTISR_DCONNI                 (_U_(0x1) << HSTISR_DCONNI_Pos)

#define HSTISR_DDISCI_Pos             1

#define HSTISR_DDISCI                 (_U_(0x1) << HSTISR_DDISCI_Pos)

#define HSTISR_RSTI_Pos               2

#define HSTISR_RSTI                   (_U_(0x1) << HSTISR_RSTI_Pos)

#define HSTISR_RSMEDI_Pos             3

#define HSTISR_RSMEDI                 (_U_(0x1) << HSTISR_RSMEDI_Pos)

#define HSTISR_RXRSMI_Pos             4

#define HSTISR_RXRSMI                 (_U_(0x1) << HSTISR_RXRSMI_Pos)

#define HSTISR_HSOFI_Pos              5

#define HSTISR_HSOFI                  (_U_(0x1) << HSTISR_HSOFI_Pos)

#define HSTISR_HWUPI_Pos              6

#define HSTISR_HWUPI                  (_U_(0x1) << HSTISR_HWUPI_Pos)

#define HSTISR_PEP_0_Pos              8

#define HSTISR_PEP_0                  (_U_(0x1) << HSTISR_PEP_0_Pos)

#define HSTISR_PEP_1_Pos              9

#define HSTISR_PEP_1                  (_U_(0x1) << HSTISR_PEP_1_Pos)

#define HSTISR_PEP_2_Pos              10

#define HSTISR_PEP_2                  (_U_(0x1) << HSTISR_PEP_2_Pos)

#define HSTISR_PEP_3_Pos              11

#define HSTISR_PEP_3                  (_U_(0x1) << HSTISR_PEP_3_Pos)

#define HSTISR_PEP_4_Pos              12

#define HSTISR_PEP_4                  (_U_(0x1) << HSTISR_PEP_4_Pos)

#define HSTISR_PEP_5_Pos              13

#define HSTISR_PEP_5                  (_U_(0x1) << HSTISR_PEP_5_Pos)

#define HSTISR_PEP_6_Pos              14

#define HSTISR_PEP_6                  (_U_(0x1) << HSTISR_PEP_6_Pos)

#define HSTISR_PEP_7_Pos              15

#define HSTISR_PEP_7                  (_U_(0x1) << HSTISR_PEP_7_Pos)

#define HSTISR_PEP_8_Pos              16

#define HSTISR_PEP_8                  (_U_(0x1) << HSTISR_PEP_8_Pos)

#define HSTISR_PEP_9_Pos              17

#define HSTISR_PEP_9                  (_U_(0x1) << HSTISR_PEP_9_Pos)

#define HSTISR_DMA_0_Pos              25

#define HSTISR_DMA_0                  (_U_(0x1) << HSTISR_DMA_0_Pos)

#define HSTISR_DMA_1_Pos              26

#define HSTISR_DMA_1                  (_U_(0x1) << HSTISR_DMA_1_Pos)

#define HSTISR_DMA_2_Pos              27

#define HSTISR_DMA_2                  (_U_(0x1) << HSTISR_DMA_2_Pos)

#define HSTISR_DMA_3_Pos              28

#define HSTISR_DMA_3                  (_U_(0x1) << HSTISR_DMA_3_Pos)

#define HSTISR_DMA_4_Pos              29

#define HSTISR_DMA_4                  (_U_(0x1) << HSTISR_DMA_4_Pos)

#define HSTISR_DMA_5_Pos              30

#define HSTISR_DMA_5                  (_U_(0x1) << HSTISR_DMA_5_Pos)

#define HSTISR_DMA_6_Pos              31

#define HSTISR_DMA_6                  (_U_(0x1) << HSTISR_DMA_6_Pos)

#define HSTISR_Msk                    _U_(0xFE03FF7F)

#define HSTISR_PEP__Pos               8

#define HSTISR_PEP_                   (_U_(0x3FF) << HSTISR_PEP__Pos)

#define HSTISR_DMA__Pos               25

#define HSTISR_DMA_                   (_U_(0x7F) << HSTISR_DMA__Pos)

/* -------- HSTICR : (USBHS Offset: 0x408) (/W 32) Host Global Interrupt Clear Register -------- */


#define HSTICR_OFFSET                 (0x408)

#define HSTICR_DCONNIC_Pos            0

#define HSTICR_DCONNIC                (_U_(0x1) << HSTICR_DCONNIC_Pos)

#define HSTICR_DDISCIC_Pos            1

#define HSTICR_DDISCIC                (_U_(0x1) << HSTICR_DDISCIC_Pos)

#define HSTICR_RSTIC_Pos              2

#define HSTICR_RSTIC                  (_U_(0x1) << HSTICR_RSTIC_Pos)

#define HSTICR_RSMEDIC_Pos            3

#define HSTICR_RSMEDIC                (_U_(0x1) << HSTICR_RSMEDIC_Pos)

#define HSTICR_RXRSMIC_Pos            4

#define HSTICR_RXRSMIC                (_U_(0x1) << HSTICR_RXRSMIC_Pos)

#define HSTICR_HSOFIC_Pos             5

#define HSTICR_HSOFIC                 (_U_(0x1) << HSTICR_HSOFIC_Pos)

#define HSTICR_HWUPIC_Pos             6

#define HSTICR_HWUPIC                 (_U_(0x1) << HSTICR_HWUPIC_Pos)

#define HSTICR_Msk                    _U_(0x7F)

/* -------- HSTIFR : (USBHS Offset: 0x40c) (/W 32) Host Global Interrupt Set Register -------- */


#define HSTIFR_OFFSET                 (0x40C)

#define HSTIFR_DCONNIS_Pos            0

#define HSTIFR_DCONNIS                (_U_(0x1) << HSTIFR_DCONNIS_Pos)

#define HSTIFR_DDISCIS_Pos            1

#define HSTIFR_DDISCIS                (_U_(0x1) << HSTIFR_DDISCIS_Pos)

#define HSTIFR_RSTIS_Pos              2

#define HSTIFR_RSTIS                  (_U_(0x1) << HSTIFR_RSTIS_Pos)

#define HSTIFR_RSMEDIS_Pos            3

#define HSTIFR_RSMEDIS                (_U_(0x1) << HSTIFR_RSMEDIS_Pos)

#define HSTIFR_RXRSMIS_Pos            4

#define HSTIFR_RXRSMIS                (_U_(0x1) << HSTIFR_RXRSMIS_Pos)

#define HSTIFR_HSOFIS_Pos             5

#define HSTIFR_HSOFIS                 (_U_(0x1) << HSTIFR_HSOFIS_Pos)

#define HSTIFR_HWUPIS_Pos             6

#define HSTIFR_HWUPIS                 (_U_(0x1) << HSTIFR_HWUPIS_Pos)

#define HSTIFR_DMA_0_Pos              25

#define HSTIFR_DMA_0                  (_U_(0x1) << HSTIFR_DMA_0_Pos)

#define HSTIFR_DMA_1_Pos              26

#define HSTIFR_DMA_1                  (_U_(0x1) << HSTIFR_DMA_1_Pos)

#define HSTIFR_DMA_2_Pos              27

#define HSTIFR_DMA_2                  (_U_(0x1) << HSTIFR_DMA_2_Pos)

#define HSTIFR_DMA_3_Pos              28

#define HSTIFR_DMA_3                  (_U_(0x1) << HSTIFR_DMA_3_Pos)

#define HSTIFR_DMA_4_Pos              29

#define HSTIFR_DMA_4                  (_U_(0x1) << HSTIFR_DMA_4_Pos)

#define HSTIFR_DMA_5_Pos              30

#define HSTIFR_DMA_5                  (_U_(0x1) << HSTIFR_DMA_5_Pos)

#define HSTIFR_DMA_6_Pos              31

#define HSTIFR_DMA_6                  (_U_(0x1) << HSTIFR_DMA_6_Pos)

#define HSTIFR_Msk                    _U_(0xFE00007F)

#define HSTIFR_DMA__Pos               25

#define HSTIFR_DMA_                   (_U_(0x7F) << HSTIFR_DMA__Pos)

/* -------- HSTIMR : (USBHS Offset: 0x410) (R/ 32) Host Global Interrupt Mask Register -------- */


#define HSTIMR_OFFSET                 (0x410)

#define HSTIMR_DCONNIE_Pos            0

#define HSTIMR_DCONNIE                (_U_(0x1) << HSTIMR_DCONNIE_Pos)

#define HSTIMR_DDISCIE_Pos            1

#define HSTIMR_DDISCIE                (_U_(0x1) << HSTIMR_DDISCIE_Pos)

#define HSTIMR_RSTIE_Pos              2

#define HSTIMR_RSTIE                  (_U_(0x1) << HSTIMR_RSTIE_Pos)

#define HSTIMR_RSMEDIE_Pos            3

#define HSTIMR_RSMEDIE                (_U_(0x1) << HSTIMR_RSMEDIE_Pos)

#define HSTIMR_RXRSMIE_Pos            4

#define HSTIMR_RXRSMIE                (_U_(0x1) << HSTIMR_RXRSMIE_Pos)

#define HSTIMR_HSOFIE_Pos             5

#define HSTIMR_HSOFIE                 (_U_(0x1) << HSTIMR_HSOFIE_Pos)

#define HSTIMR_HWUPIE_Pos             6

#define HSTIMR_HWUPIE                 (_U_(0x1) << HSTIMR_HWUPIE_Pos)

#define HSTIMR_PEP_0_Pos              8

#define HSTIMR_PEP_0                  (_U_(0x1) << HSTIMR_PEP_0_Pos)

#define HSTIMR_PEP_1_Pos              9

#define HSTIMR_PEP_1                  (_U_(0x1) << HSTIMR_PEP_1_Pos)

#define HSTIMR_PEP_2_Pos              10

#define HSTIMR_PEP_2                  (_U_(0x1) << HSTIMR_PEP_2_Pos)

#define HSTIMR_PEP_3_Pos              11

#define HSTIMR_PEP_3                  (_U_(0x1) << HSTIMR_PEP_3_Pos)

#define HSTIMR_PEP_4_Pos              12

#define HSTIMR_PEP_4                  (_U_(0x1) << HSTIMR_PEP_4_Pos)

#define HSTIMR_PEP_5_Pos              13

#define HSTIMR_PEP_5                  (_U_(0x1) << HSTIMR_PEP_5_Pos)

#define HSTIMR_PEP_6_Pos              14

#define HSTIMR_PEP_6                  (_U_(0x1) << HSTIMR_PEP_6_Pos)

#define HSTIMR_PEP_7_Pos              15

#define HSTIMR_PEP_7                  (_U_(0x1) << HSTIMR_PEP_7_Pos)

#define HSTIMR_PEP_8_Pos              16

#define HSTIMR_PEP_8                  (_U_(0x1) << HSTIMR_PEP_8_Pos)

#define HSTIMR_PEP_9_Pos              17

#define HSTIMR_PEP_9                  (_U_(0x1) << HSTIMR_PEP_9_Pos)

#define HSTIMR_DMA_0_Pos              25

#define HSTIMR_DMA_0                  (_U_(0x1) << HSTIMR_DMA_0_Pos)

#define HSTIMR_DMA_1_Pos              26

#define HSTIMR_DMA_1                  (_U_(0x1) << HSTIMR_DMA_1_Pos)

#define HSTIMR_DMA_2_Pos              27

#define HSTIMR_DMA_2                  (_U_(0x1) << HSTIMR_DMA_2_Pos)

#define HSTIMR_DMA_3_Pos              28

#define HSTIMR_DMA_3                  (_U_(0x1) << HSTIMR_DMA_3_Pos)

#define HSTIMR_DMA_4_Pos              29

#define HSTIMR_DMA_4                  (_U_(0x1) << HSTIMR_DMA_4_Pos)

#define HSTIMR_DMA_5_Pos              30

#define HSTIMR_DMA_5                  (_U_(0x1) << HSTIMR_DMA_5_Pos)

#define HSTIMR_DMA_6_Pos              31

#define HSTIMR_DMA_6                  (_U_(0x1) << HSTIMR_DMA_6_Pos)

#define HSTIMR_Msk                    _U_(0xFE03FF7F)

#define HSTIMR_PEP__Pos               8

#define HSTIMR_PEP_                   (_U_(0x3FF) << HSTIMR_PEP__Pos)

#define HSTIMR_DMA__Pos               25

#define HSTIMR_DMA_                   (_U_(0x7F) << HSTIMR_DMA__Pos)

/* -------- HSTIDR : (USBHS Offset: 0x414) (/W 32) Host Global Interrupt Disable Register -------- */


#define HSTIDR_OFFSET                 (0x414)

#define HSTIDR_DCONNIEC_Pos           0

#define HSTIDR_DCONNIEC               (_U_(0x1) << HSTIDR_DCONNIEC_Pos)

#define HSTIDR_DDISCIEC_Pos           1

#define HSTIDR_DDISCIEC               (_U_(0x1) << HSTIDR_DDISCIEC_Pos)

#define HSTIDR_RSTIEC_Pos             2

#define HSTIDR_RSTIEC                 (_U_(0x1) << HSTIDR_RSTIEC_Pos)

#define HSTIDR_RSMEDIEC_Pos           3

#define HSTIDR_RSMEDIEC               (_U_(0x1) << HSTIDR_RSMEDIEC_Pos)

#define HSTIDR_RXRSMIEC_Pos           4

#define HSTIDR_RXRSMIEC               (_U_(0x1) << HSTIDR_RXRSMIEC_Pos)

#define HSTIDR_HSOFIEC_Pos            5

#define HSTIDR_HSOFIEC                (_U_(0x1) << HSTIDR_HSOFIEC_Pos)

#define HSTIDR_HWUPIEC_Pos            6

#define HSTIDR_HWUPIEC                (_U_(0x1) << HSTIDR_HWUPIEC_Pos)

#define HSTIDR_PEP_0_Pos              8

#define HSTIDR_PEP_0                  (_U_(0x1) << HSTIDR_PEP_0_Pos)

#define HSTIDR_PEP_1_Pos              9

#define HSTIDR_PEP_1                  (_U_(0x1) << HSTIDR_PEP_1_Pos)

#define HSTIDR_PEP_2_Pos              10

#define HSTIDR_PEP_2                  (_U_(0x1) << HSTIDR_PEP_2_Pos)

#define HSTIDR_PEP_3_Pos              11

#define HSTIDR_PEP_3                  (_U_(0x1) << HSTIDR_PEP_3_Pos)

#define HSTIDR_PEP_4_Pos              12

#define HSTIDR_PEP_4                  (_U_(0x1) << HSTIDR_PEP_4_Pos)

#define HSTIDR_PEP_5_Pos              13

#define HSTIDR_PEP_5                  (_U_(0x1) << HSTIDR_PEP_5_Pos)

#define HSTIDR_PEP_6_Pos              14

#define HSTIDR_PEP_6                  (_U_(0x1) << HSTIDR_PEP_6_Pos)

#define HSTIDR_PEP_7_Pos              15

#define HSTIDR_PEP_7                  (_U_(0x1) << HSTIDR_PEP_7_Pos)

#define HSTIDR_PEP_8_Pos              16

#define HSTIDR_PEP_8                  (_U_(0x1) << HSTIDR_PEP_8_Pos)

#define HSTIDR_PEP_9_Pos              17

#define HSTIDR_PEP_9                  (_U_(0x1) << HSTIDR_PEP_9_Pos)

#define HSTIDR_DMA_0_Pos              25

#define HSTIDR_DMA_0                  (_U_(0x1) << HSTIDR_DMA_0_Pos)

#define HSTIDR_DMA_1_Pos              26

#define HSTIDR_DMA_1                  (_U_(0x1) << HSTIDR_DMA_1_Pos)

#define HSTIDR_DMA_2_Pos              27

#define HSTIDR_DMA_2                  (_U_(0x1) << HSTIDR_DMA_2_Pos)

#define HSTIDR_DMA_3_Pos              28

#define HSTIDR_DMA_3                  (_U_(0x1) << HSTIDR_DMA_3_Pos)

#define HSTIDR_DMA_4_Pos              29

#define HSTIDR_DMA_4                  (_U_(0x1) << HSTIDR_DMA_4_Pos)

#define HSTIDR_DMA_5_Pos              30

#define HSTIDR_DMA_5                  (_U_(0x1) << HSTIDR_DMA_5_Pos)

#define HSTIDR_DMA_6_Pos              31

#define HSTIDR_DMA_6                  (_U_(0x1) << HSTIDR_DMA_6_Pos)

#define HSTIDR_Msk                    _U_(0xFE03FF7F)

#define HSTIDR_PEP__Pos               8

#define HSTIDR_PEP_                   (_U_(0x3FF) << HSTIDR_PEP__Pos)

#define HSTIDR_DMA__Pos               25

#define HSTIDR_DMA_                   (_U_(0x7F) << HSTIDR_DMA__Pos)

/* -------- HSTIER : (USBHS Offset: 0x418) (/W 32) Host Global Interrupt Enable Register -------- */


#define HSTIER_OFFSET                 (0x418)

#define HSTIER_DCONNIES_Pos           0

#define HSTIER_DCONNIES               (_U_(0x1) << HSTIER_DCONNIES_Pos)

#define HSTIER_DDISCIES_Pos           1

#define HSTIER_DDISCIES               (_U_(0x1) << HSTIER_DDISCIES_Pos)

#define HSTIER_RSTIES_Pos             2

#define HSTIER_RSTIES                 (_U_(0x1) << HSTIER_RSTIES_Pos)

#define HSTIER_RSMEDIES_Pos           3

#define HSTIER_RSMEDIES               (_U_(0x1) << HSTIER_RSMEDIES_Pos)

#define HSTIER_RXRSMIES_Pos           4

#define HSTIER_RXRSMIES               (_U_(0x1) << HSTIER_RXRSMIES_Pos)

#define HSTIER_HSOFIES_Pos            5

#define HSTIER_HSOFIES                (_U_(0x1) << HSTIER_HSOFIES_Pos)

#define HSTIER_HWUPIES_Pos            6

#define HSTIER_HWUPIES                (_U_(0x1) << HSTIER_HWUPIES_Pos)

#define HSTIER_PEP_0_Pos              8

#define HSTIER_PEP_0                  (_U_(0x1) << HSTIER_PEP_0_Pos)

#define HSTIER_PEP_1_Pos              9

#define HSTIER_PEP_1                  (_U_(0x1) << HSTIER_PEP_1_Pos)

#define HSTIER_PEP_2_Pos              10

#define HSTIER_PEP_2                  (_U_(0x1) << HSTIER_PEP_2_Pos)

#define HSTIER_PEP_3_Pos              11

#define HSTIER_PEP_3                  (_U_(0x1) << HSTIER_PEP_3_Pos)

#define HSTIER_PEP_4_Pos              12

#define HSTIER_PEP_4                  (_U_(0x1) << HSTIER_PEP_4_Pos)

#define HSTIER_PEP_5_Pos              13

#define HSTIER_PEP_5                  (_U_(0x1) << HSTIER_PEP_5_Pos)

#define HSTIER_PEP_6_Pos              14

#define HSTIER_PEP_6                  (_U_(0x1) << HSTIER_PEP_6_Pos)

#define HSTIER_PEP_7_Pos              15

#define HSTIER_PEP_7                  (_U_(0x1) << HSTIER_PEP_7_Pos)

#define HSTIER_PEP_8_Pos              16

#define HSTIER_PEP_8                  (_U_(0x1) << HSTIER_PEP_8_Pos)

#define HSTIER_PEP_9_Pos              17

#define HSTIER_PEP_9                  (_U_(0x1) << HSTIER_PEP_9_Pos)

#define HSTIER_DMA_0_Pos              25

#define HSTIER_DMA_0                  (_U_(0x1) << HSTIER_DMA_0_Pos)

#define HSTIER_DMA_1_Pos              26

#define HSTIER_DMA_1                  (_U_(0x1) << HSTIER_DMA_1_Pos)

#define HSTIER_DMA_2_Pos              27

#define HSTIER_DMA_2                  (_U_(0x1) << HSTIER_DMA_2_Pos)

#define HSTIER_DMA_3_Pos              28

#define HSTIER_DMA_3                  (_U_(0x1) << HSTIER_DMA_3_Pos)

#define HSTIER_DMA_4_Pos              29

#define HSTIER_DMA_4                  (_U_(0x1) << HSTIER_DMA_4_Pos)

#define HSTIER_DMA_5_Pos              30

#define HSTIER_DMA_5                  (_U_(0x1) << HSTIER_DMA_5_Pos)

#define HSTIER_DMA_6_Pos              31

#define HSTIER_DMA_6                  (_U_(0x1) << HSTIER_DMA_6_Pos)

#define HSTIER_Msk                    _U_(0xFE03FF7F)

#define HSTIER_PEP__Pos               8

#define HSTIER_PEP_                   (_U_(0x3FF) << HSTIER_PEP__Pos)

#define HSTIER_DMA__Pos               25

#define HSTIER_DMA_                   (_U_(0x7F) << HSTIER_DMA__Pos)

/* -------- HSTPIP : (USBHS Offset: 0x41c) (R/W 32) Host Pipe Register -------- */


#define HSTPIP_OFFSET                 (0x41C)

#define HSTPIP_PEN0_Pos               0

#define HSTPIP_PEN0                   (_U_(0x1) << HSTPIP_PEN0_Pos)

#define HSTPIP_PEN1_Pos               1

#define HSTPIP_PEN1                   (_U_(0x1) << HSTPIP_PEN1_Pos)

#define HSTPIP_PEN2_Pos               2

#define HSTPIP_PEN2                   (_U_(0x1) << HSTPIP_PEN2_Pos)

#define HSTPIP_PEN3_Pos               3

#define HSTPIP_PEN3                   (_U_(0x1) << HSTPIP_PEN3_Pos)

#define HSTPIP_PEN4_Pos               4

#define HSTPIP_PEN4                   (_U_(0x1) << HSTPIP_PEN4_Pos)

#define HSTPIP_PEN5_Pos               5

#define HSTPIP_PEN5                   (_U_(0x1) << HSTPIP_PEN5_Pos)

#define HSTPIP_PEN6_Pos               6

#define HSTPIP_PEN6                   (_U_(0x1) << HSTPIP_PEN6_Pos)

#define HSTPIP_PEN7_Pos               7

#define HSTPIP_PEN7                   (_U_(0x1) << HSTPIP_PEN7_Pos)

#define HSTPIP_PEN8_Pos               8

#define HSTPIP_PEN8                   (_U_(0x1) << HSTPIP_PEN8_Pos)

#define HSTPIP_PRST0_Pos              16

#define HSTPIP_PRST0                  (_U_(0x1) << HSTPIP_PRST0_Pos)

#define HSTPIP_PRST1_Pos              17

#define HSTPIP_PRST1                  (_U_(0x1) << HSTPIP_PRST1_Pos)

#define HSTPIP_PRST2_Pos              18

#define HSTPIP_PRST2                  (_U_(0x1) << HSTPIP_PRST2_Pos)

#define HSTPIP_PRST3_Pos              19

#define HSTPIP_PRST3                  (_U_(0x1) << HSTPIP_PRST3_Pos)

#define HSTPIP_PRST4_Pos              20

#define HSTPIP_PRST4                  (_U_(0x1) << HSTPIP_PRST4_Pos)

#define HSTPIP_PRST5_Pos              21

#define HSTPIP_PRST5                  (_U_(0x1) << HSTPIP_PRST5_Pos)

#define HSTPIP_PRST6_Pos              22

#define HSTPIP_PRST6                  (_U_(0x1) << HSTPIP_PRST6_Pos)

#define HSTPIP_PRST7_Pos              23

#define HSTPIP_PRST7                  (_U_(0x1) << HSTPIP_PRST7_Pos)

#define HSTPIP_PRST8_Pos              24

#define HSTPIP_PRST8                  (_U_(0x1) << HSTPIP_PRST8_Pos)

#define HSTPIP_Msk                    _U_(0x1FF01FF)

#define HSTPIP_PEN_Pos                0

#define HSTPIP_PEN                    (_U_(0x1FF) << HSTPIP_PEN_Pos)

#define HSTPIP_PRST_Pos               16

#define HSTPIP_PRST                   (_U_(0x1FF) << HSTPIP_PRST_Pos)

/* -------- HSTFNUM : (USBHS Offset: 0x420) (R/W 32) Host Frame Number Register -------- */


#define HSTFNUM_OFFSET                (0x420)

#define HSTFNUM_MFNUM_Pos             0

#define HSTFNUM_MFNUM                 (_U_(0x7) << HSTFNUM_MFNUM_Pos)

#define HSTFNUM_FNUM_Pos              3

#define HSTFNUM_FNUM                  (_U_(0x7FF) << HSTFNUM_FNUM_Pos)

#define HSTFNUM_FLENHIGH_Pos          16

#define HSTFNUM_FLENHIGH              (_U_(0xFF) << HSTFNUM_FLENHIGH_Pos)

#define HSTFNUM_Msk                   _U_(0xFF3FFF)

/* -------- HSTADDR1 : (USBHS Offset: 0x424) (R/W 32) Host Address 1 Register -------- */


#define HSTADDR1_OFFSET               (0x424)

#define HSTADDR1_HSTADDRP0_Pos        0

#define HSTADDR1_HSTADDRP0            (_U_(0x7F) << HSTADDR1_HSTADDRP0_Pos)

#define HSTADDR1_HSTADDRP1_Pos        8

#define HSTADDR1_HSTADDRP1            (_U_(0x7F) << HSTADDR1_HSTADDRP1_Pos)

#define HSTADDR1_HSTADDRP2_Pos        16

#define HSTADDR1_HSTADDRP2            (_U_(0x7F) << HSTADDR1_HSTADDRP2_Pos)

#define HSTADDR1_HSTADDRP3_Pos        24

#define HSTADDR1_HSTADDRP3            (_U_(0x7F) << HSTADDR1_HSTADDRP3_Pos)

#define HSTADDR1_Msk                  _U_(0x7F7F7F7F)

/* -------- HSTADDR2 : (USBHS Offset: 0x428) (R/W 32) Host Address 2 Register -------- */


#define HSTADDR2_OFFSET               (0x428)

#define HSTADDR2_HSTADDRP4_Pos        0

#define HSTADDR2_HSTADDRP4            (_U_(0x7F) << HSTADDR2_HSTADDRP4_Pos)

#define HSTADDR2_HSTADDRP5_Pos        8

#define HSTADDR2_HSTADDRP5            (_U_(0x7F) << HSTADDR2_HSTADDRP5_Pos)

#define HSTADDR2_HSTADDRP6_Pos        16

#define HSTADDR2_HSTADDRP6            (_U_(0x7F) << HSTADDR2_HSTADDRP6_Pos)

#define HSTADDR2_HSTADDRP7_Pos        24

#define HSTADDR2_HSTADDRP7            (_U_(0x7F) << HSTADDR2_HSTADDRP7_Pos)

#define HSTADDR2_Msk                  _U_(0x7F7F7F7F)

/* -------- HSTADDR3 : (USBHS Offset: 0x42c) (R/W 32) Host Address 3 Register -------- */


#define HSTADDR3_OFFSET               (0x42C)

#define HSTADDR3_HSTADDRP8_Pos        0

#define HSTADDR3_HSTADDRP8            (_U_(0x7F) << HSTADDR3_HSTADDRP8_Pos)

#define HSTADDR3_HSTADDRP9_Pos        8

#define HSTADDR3_HSTADDRP9            (_U_(0x7F) << HSTADDR3_HSTADDRP9_Pos)

#define HSTADDR3_Msk                  _U_(0x7F7F)

/* -------- HSTPIPCFG : (USBHS Offset: 0x500) (R/W 32) Host Pipe Configuration Register -------- */


#define HSTPIPCFG_OFFSET              (0x500)

#define HSTPIPCFG_ALLOC_Pos           1

#define HSTPIPCFG_ALLOC               (_U_(0x1) << HSTPIPCFG_ALLOC_Pos)

#define HSTPIPCFG_PBK_Pos             2

#define HSTPIPCFG_PBK                 (_U_(0x3) << HSTPIPCFG_PBK_Pos)

#define   HSTPIPCFG_PBK_1_BANK_Val    _U_(0x0)

#define   HSTPIPCFG_PBK_2_BANK_Val    _U_(0x1)

#define   HSTPIPCFG_PBK_3_BANK_Val    _U_(0x2)

#define HSTPIPCFG_PBK_1_BANK          (HSTPIPCFG_PBK_1_BANK_Val << HSTPIPCFG_PBK_Pos)

#define HSTPIPCFG_PBK_2_BANK          (HSTPIPCFG_PBK_2_BANK_Val << HSTPIPCFG_PBK_Pos)

#define HSTPIPCFG_PBK_3_BANK          (HSTPIPCFG_PBK_3_BANK_Val << HSTPIPCFG_PBK_Pos)

#define HSTPIPCFG_PSIZE_Pos           4

#define HSTPIPCFG_PSIZE               (_U_(0x7) << HSTPIPCFG_PSIZE_Pos)

#define   HSTPIPCFG_PSIZE_8_BYTE_Val  _U_(0x0)

#define   HSTPIPCFG_PSIZE_16_BYTE_Val _U_(0x1)

#define   HSTPIPCFG_PSIZE_32_BYTE_Val _U_(0x2)

#define   HSTPIPCFG_PSIZE_64_BYTE_Val _U_(0x3)

#define   HSTPIPCFG_PSIZE_128_BYTE_Val _U_(0x4)

#define   HSTPIPCFG_PSIZE_256_BYTE_Val _U_(0x5)

#define   HSTPIPCFG_PSIZE_512_BYTE_Val _U_(0x6)

#define   HSTPIPCFG_PSIZE_1024_BYTE_Val _U_(0x7)

#define HSTPIPCFG_PSIZE_8_BYTE        (HSTPIPCFG_PSIZE_8_BYTE_Val << HSTPIPCFG_PSIZE_Pos)

#define HSTPIPCFG_PSIZE_16_BYTE       (HSTPIPCFG_PSIZE_16_BYTE_Val << HSTPIPCFG_PSIZE_Pos)

#define HSTPIPCFG_PSIZE_32_BYTE       (HSTPIPCFG_PSIZE_32_BYTE_Val << HSTPIPCFG_PSIZE_Pos)

#define HSTPIPCFG_PSIZE_64_BYTE       (HSTPIPCFG_PSIZE_64_BYTE_Val << HSTPIPCFG_PSIZE_Pos)

#define HSTPIPCFG_PSIZE_128_BYTE      (HSTPIPCFG_PSIZE_128_BYTE_Val << HSTPIPCFG_PSIZE_Pos)

#define HSTPIPCFG_PSIZE_256_BYTE      (HSTPIPCFG_PSIZE_256_BYTE_Val << HSTPIPCFG_PSIZE_Pos)

#define HSTPIPCFG_PSIZE_512_BYTE      (HSTPIPCFG_PSIZE_512_BYTE_Val << HSTPIPCFG_PSIZE_Pos)

#define HSTPIPCFG_PSIZE_1024_BYTE     (HSTPIPCFG_PSIZE_1024_BYTE_Val << HSTPIPCFG_PSIZE_Pos)

#define HSTPIPCFG_PTOKEN_Pos          8

#define HSTPIPCFG_PTOKEN              (_U_(0x3) << HSTPIPCFG_PTOKEN_Pos)

#define   HSTPIPCFG_PTOKEN_SETUP_Val  _U_(0x0)

#define   HSTPIPCFG_PTOKEN_IN_Val     _U_(0x1)

#define   HSTPIPCFG_PTOKEN_OUT_Val    _U_(0x2)

#define HSTPIPCFG_PTOKEN_SETUP        (HSTPIPCFG_PTOKEN_SETUP_Val << HSTPIPCFG_PTOKEN_Pos)

#define HSTPIPCFG_PTOKEN_IN           (HSTPIPCFG_PTOKEN_IN_Val << HSTPIPCFG_PTOKEN_Pos)

#define HSTPIPCFG_PTOKEN_OUT          (HSTPIPCFG_PTOKEN_OUT_Val << HSTPIPCFG_PTOKEN_Pos)

#define HSTPIPCFG_AUTOSW_Pos          10

#define HSTPIPCFG_AUTOSW              (_U_(0x1) << HSTPIPCFG_AUTOSW_Pos)

#define HSTPIPCFG_PTYPE_Pos           12

#define HSTPIPCFG_PTYPE               (_U_(0x3) << HSTPIPCFG_PTYPE_Pos)

#define   HSTPIPCFG_PTYPE_CTRL_Val    _U_(0x0)

#define   HSTPIPCFG_PTYPE_ISO_Val     _U_(0x1)

#define   HSTPIPCFG_PTYPE_BLK_Val     _U_(0x2)

#define   HSTPIPCFG_PTYPE_INTRPT_Val  _U_(0x3)

#define HSTPIPCFG_PTYPE_CTRL          (HSTPIPCFG_PTYPE_CTRL_Val << HSTPIPCFG_PTYPE_Pos)

#define HSTPIPCFG_PTYPE_ISO           (HSTPIPCFG_PTYPE_ISO_Val << HSTPIPCFG_PTYPE_Pos)

#define HSTPIPCFG_PTYPE_BLK           (HSTPIPCFG_PTYPE_BLK_Val << HSTPIPCFG_PTYPE_Pos)

#define HSTPIPCFG_PTYPE_INTRPT        (HSTPIPCFG_PTYPE_INTRPT_Val << HSTPIPCFG_PTYPE_Pos)

#define HSTPIPCFG_PEPNUM_Pos          16

#define HSTPIPCFG_PEPNUM              (_U_(0xF) << HSTPIPCFG_PEPNUM_Pos)

#define HSTPIPCFG_INTFRQ_Pos          24

#define HSTPIPCFG_INTFRQ              (_U_(0xFF) << HSTPIPCFG_INTFRQ_Pos)

#define HSTPIPCFG_Msk                 _U_(0xFF0F377E)

/* CTRL_BULK mode */

#define HSTPIPCFG_CTRL_BULK_PINGEN_Pos 20

#define HSTPIPCFG_CTRL_BULK_PINGEN     (_U_(0x1) << HSTPIPCFG_CTRL_BULK_PINGEN_Pos)

#define HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos 24

#define HSTPIPCFG_CTRL_BULK_BINTERVAL     (_U_(0xFF) << HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos)

#define HSTPIPCFG_CTRL_BULK_Msk       _U_(0xFF100000)

/* -------- HSTPIPISR : (USBHS Offset: 0x530) (R/ 32) Host Pipe Status Register -------- */


#define HSTPIPISR_OFFSET              (0x530)

#define HSTPIPISR_RXINI_Pos           0

#define HSTPIPISR_RXINI               (_U_(0x1) << HSTPIPISR_RXINI_Pos)

#define HSTPIPISR_TXOUTI_Pos          1

#define HSTPIPISR_TXOUTI              (_U_(0x1) << HSTPIPISR_TXOUTI_Pos)

#define HSTPIPISR_PERRI_Pos           3

#define HSTPIPISR_PERRI               (_U_(0x1) << HSTPIPISR_PERRI_Pos)

#define HSTPIPISR_NAKEDI_Pos          4

#define HSTPIPISR_NAKEDI              (_U_(0x1) << HSTPIPISR_NAKEDI_Pos)

#define HSTPIPISR_OVERFI_Pos          5

#define HSTPIPISR_OVERFI              (_U_(0x1) << HSTPIPISR_OVERFI_Pos)

#define HSTPIPISR_SHORTPACKETI_Pos    7

#define HSTPIPISR_SHORTPACKETI        (_U_(0x1) << HSTPIPISR_SHORTPACKETI_Pos)

#define HSTPIPISR_DTSEQ_Pos           8

#define HSTPIPISR_DTSEQ               (_U_(0x3) << HSTPIPISR_DTSEQ_Pos)

#define   HSTPIPISR_DTSEQ_DATA0_Val   _U_(0x0)

#define   HSTPIPISR_DTSEQ_DATA1_Val   _U_(0x1)

#define HSTPIPISR_DTSEQ_DATA0         (HSTPIPISR_DTSEQ_DATA0_Val << HSTPIPISR_DTSEQ_Pos)

#define HSTPIPISR_DTSEQ_DATA1         (HSTPIPISR_DTSEQ_DATA1_Val << HSTPIPISR_DTSEQ_Pos)

#define HSTPIPISR_NBUSYBK_Pos         12

#define HSTPIPISR_NBUSYBK             (_U_(0x3) << HSTPIPISR_NBUSYBK_Pos)

#define   HSTPIPISR_NBUSYBK_0_BUSY_Val _U_(0x0)

#define   HSTPIPISR_NBUSYBK_1_BUSY_Val _U_(0x1)

#define   HSTPIPISR_NBUSYBK_2_BUSY_Val _U_(0x2)

#define   HSTPIPISR_NBUSYBK_3_BUSY_Val _U_(0x3)

#define HSTPIPISR_NBUSYBK_0_BUSY      (HSTPIPISR_NBUSYBK_0_BUSY_Val << HSTPIPISR_NBUSYBK_Pos)

#define HSTPIPISR_NBUSYBK_1_BUSY      (HSTPIPISR_NBUSYBK_1_BUSY_Val << HSTPIPISR_NBUSYBK_Pos)

#define HSTPIPISR_NBUSYBK_2_BUSY      (HSTPIPISR_NBUSYBK_2_BUSY_Val << HSTPIPISR_NBUSYBK_Pos)

#define HSTPIPISR_NBUSYBK_3_BUSY      (HSTPIPISR_NBUSYBK_3_BUSY_Val << HSTPIPISR_NBUSYBK_Pos)

#define HSTPIPISR_CURRBK_Pos          14

#define HSTPIPISR_CURRBK              (_U_(0x3) << HSTPIPISR_CURRBK_Pos)

#define   HSTPIPISR_CURRBK_BANK0_Val  _U_(0x0)

#define   HSTPIPISR_CURRBK_BANK1_Val  _U_(0x1)

#define   HSTPIPISR_CURRBK_BANK2_Val  _U_(0x2)

#define HSTPIPISR_CURRBK_BANK0        (HSTPIPISR_CURRBK_BANK0_Val << HSTPIPISR_CURRBK_Pos)

#define HSTPIPISR_CURRBK_BANK1        (HSTPIPISR_CURRBK_BANK1_Val << HSTPIPISR_CURRBK_Pos)

#define HSTPIPISR_CURRBK_BANK2        (HSTPIPISR_CURRBK_BANK2_Val << HSTPIPISR_CURRBK_Pos)

#define HSTPIPISR_RWALL_Pos           16

#define HSTPIPISR_RWALL               (_U_(0x1) << HSTPIPISR_RWALL_Pos)

#define HSTPIPISR_CFGOK_Pos           18

#define HSTPIPISR_CFGOK               (_U_(0x1) << HSTPIPISR_CFGOK_Pos)

#define HSTPIPISR_PBYCT_Pos           20

#define HSTPIPISR_PBYCT               (_U_(0x7FF) << HSTPIPISR_PBYCT_Pos)

#define HSTPIPISR_Msk                 _U_(0x7FF5F3BB)

/* CTRL mode */

#define HSTPIPISR_CTRL_TXSTPI_Pos     2

#define HSTPIPISR_CTRL_TXSTPI         (_U_(0x1) << HSTPIPISR_CTRL_TXSTPI_Pos)

#define HSTPIPISR_CTRL_RXSTALLDI_Pos  6

#define HSTPIPISR_CTRL_RXSTALLDI      (_U_(0x1) << HSTPIPISR_CTRL_RXSTALLDI_Pos)

#define HSTPIPISR_CTRL_Msk            _U_(0x44)

/* ISO mode */

#define HSTPIPISR_ISO_UNDERFI_Pos     2

#define HSTPIPISR_ISO_UNDERFI         (_U_(0x1) << HSTPIPISR_ISO_UNDERFI_Pos)

#define HSTPIPISR_ISO_CRCERRI_Pos     6

#define HSTPIPISR_ISO_CRCERRI         (_U_(0x1) << HSTPIPISR_ISO_CRCERRI_Pos)

#define HSTPIPISR_ISO_Msk             _U_(0x44)

/* BLK mode */

#define HSTPIPISR_BLK_TXSTPI_Pos      2

#define HSTPIPISR_BLK_TXSTPI          (_U_(0x1) << HSTPIPISR_BLK_TXSTPI_Pos)

#define HSTPIPISR_BLK_RXSTALLDI_Pos   6

#define HSTPIPISR_BLK_RXSTALLDI       (_U_(0x1) << HSTPIPISR_BLK_RXSTALLDI_Pos)

#define HSTPIPISR_BLK_Msk             _U_(0x44)

/* INTRPT mode */

#define HSTPIPISR_INTRPT_UNDERFI_Pos  2

#define HSTPIPISR_INTRPT_UNDERFI      (_U_(0x1) << HSTPIPISR_INTRPT_UNDERFI_Pos)

#define HSTPIPISR_INTRPT_RXSTALLDI_Pos 6

#define HSTPIPISR_INTRPT_RXSTALLDI     (_U_(0x1) << HSTPIPISR_INTRPT_RXSTALLDI_Pos)

#define HSTPIPISR_INTRPT_Msk          _U_(0x44)

/* -------- HSTPIPICR : (USBHS Offset: 0x560) (/W 32) Host Pipe Clear Register -------- */


#define HSTPIPICR_OFFSET              (0x560)

#define HSTPIPICR_RXINIC_Pos          0

#define HSTPIPICR_RXINIC              (_U_(0x1) << HSTPIPICR_RXINIC_Pos)

#define HSTPIPICR_TXOUTIC_Pos         1

#define HSTPIPICR_TXOUTIC             (_U_(0x1) << HSTPIPICR_TXOUTIC_Pos)

#define HSTPIPICR_NAKEDIC_Pos         4

#define HSTPIPICR_NAKEDIC             (_U_(0x1) << HSTPIPICR_NAKEDIC_Pos)

#define HSTPIPICR_OVERFIC_Pos         5

#define HSTPIPICR_OVERFIC             (_U_(0x1) << HSTPIPICR_OVERFIC_Pos)

#define HSTPIPICR_SHORTPACKETIC_Pos   7

#define HSTPIPICR_SHORTPACKETIC       (_U_(0x1) << HSTPIPICR_SHORTPACKETIC_Pos)

#define HSTPIPICR_Msk                 _U_(0xB3)

/* CTRL mode */

#define HSTPIPICR_CTRL_TXSTPIC_Pos    2

#define HSTPIPICR_CTRL_TXSTPIC        (_U_(0x1) << HSTPIPICR_CTRL_TXSTPIC_Pos)

#define HSTPIPICR_CTRL_RXSTALLDIC_Pos 6

#define HSTPIPICR_CTRL_RXSTALLDIC     (_U_(0x1) << HSTPIPICR_CTRL_RXSTALLDIC_Pos)

#define HSTPIPICR_CTRL_Msk            _U_(0x44)

/* ISO mode */

#define HSTPIPICR_ISO_UNDERFIC_Pos    2

#define HSTPIPICR_ISO_UNDERFIC        (_U_(0x1) << HSTPIPICR_ISO_UNDERFIC_Pos)

#define HSTPIPICR_ISO_CRCERRIC_Pos    6

#define HSTPIPICR_ISO_CRCERRIC        (_U_(0x1) << HSTPIPICR_ISO_CRCERRIC_Pos)

#define HSTPIPICR_ISO_Msk             _U_(0x44)

/* BLK mode */

#define HSTPIPICR_BLK_TXSTPIC_Pos     2

#define HSTPIPICR_BLK_TXSTPIC         (_U_(0x1) << HSTPIPICR_BLK_TXSTPIC_Pos)

#define HSTPIPICR_BLK_RXSTALLDIC_Pos  6

#define HSTPIPICR_BLK_RXSTALLDIC      (_U_(0x1) << HSTPIPICR_BLK_RXSTALLDIC_Pos)

#define HSTPIPICR_BLK_Msk             _U_(0x44)

/* INTRPT mode */

#define HSTPIPICR_INTRPT_UNDERFIC_Pos 2

#define HSTPIPICR_INTRPT_UNDERFIC     (_U_(0x1) << HSTPIPICR_INTRPT_UNDERFIC_Pos)

#define HSTPIPICR_INTRPT_RXSTALLDIC_Pos 6

#define HSTPIPICR_INTRPT_RXSTALLDIC     (_U_(0x1) << HSTPIPICR_INTRPT_RXSTALLDIC_Pos)

#define HSTPIPICR_INTRPT_Msk          _U_(0x44)

/* -------- HSTPIPIFR : (USBHS Offset: 0x590) (/W 32) Host Pipe Set Register -------- */


#define HSTPIPIFR_OFFSET              (0x590)

#define HSTPIPIFR_RXINIS_Pos          0

#define HSTPIPIFR_RXINIS              (_U_(0x1) << HSTPIPIFR_RXINIS_Pos)

#define HSTPIPIFR_TXOUTIS_Pos         1

#define HSTPIPIFR_TXOUTIS             (_U_(0x1) << HSTPIPIFR_TXOUTIS_Pos)

#define HSTPIPIFR_PERRIS_Pos          3

#define HSTPIPIFR_PERRIS              (_U_(0x1) << HSTPIPIFR_PERRIS_Pos)

#define HSTPIPIFR_NAKEDIS_Pos         4

#define HSTPIPIFR_NAKEDIS             (_U_(0x1) << HSTPIPIFR_NAKEDIS_Pos)

#define HSTPIPIFR_OVERFIS_Pos         5

#define HSTPIPIFR_OVERFIS             (_U_(0x1) << HSTPIPIFR_OVERFIS_Pos)

#define HSTPIPIFR_SHORTPACKETIS_Pos   7

#define HSTPIPIFR_SHORTPACKETIS       (_U_(0x1) << HSTPIPIFR_SHORTPACKETIS_Pos)

#define HSTPIPIFR_NBUSYBKS_Pos        12

#define HSTPIPIFR_NBUSYBKS            (_U_(0x1) << HSTPIPIFR_NBUSYBKS_Pos)

#define HSTPIPIFR_Msk                 _U_(0x10BB)

/* CTRL mode */

#define HSTPIPIFR_CTRL_TXSTPIS_Pos    2

#define HSTPIPIFR_CTRL_TXSTPIS        (_U_(0x1) << HSTPIPIFR_CTRL_TXSTPIS_Pos)

#define HSTPIPIFR_CTRL_RXSTALLDIS_Pos 6

#define HSTPIPIFR_CTRL_RXSTALLDIS     (_U_(0x1) << HSTPIPIFR_CTRL_RXSTALLDIS_Pos)

#define HSTPIPIFR_CTRL_Msk            _U_(0x44)

/* ISO mode */

#define HSTPIPIFR_ISO_UNDERFIS_Pos    2

#define HSTPIPIFR_ISO_UNDERFIS        (_U_(0x1) << HSTPIPIFR_ISO_UNDERFIS_Pos)

#define HSTPIPIFR_ISO_CRCERRIS_Pos    6

#define HSTPIPIFR_ISO_CRCERRIS        (_U_(0x1) << HSTPIPIFR_ISO_CRCERRIS_Pos)

#define HSTPIPIFR_ISO_Msk             _U_(0x44)

/* BLK mode */

#define HSTPIPIFR_BLK_TXSTPIS_Pos     2

#define HSTPIPIFR_BLK_TXSTPIS         (_U_(0x1) << HSTPIPIFR_BLK_TXSTPIS_Pos)

#define HSTPIPIFR_BLK_RXSTALLDIS_Pos  6

#define HSTPIPIFR_BLK_RXSTALLDIS      (_U_(0x1) << HSTPIPIFR_BLK_RXSTALLDIS_Pos)

#define HSTPIPIFR_BLK_Msk             _U_(0x44)

/* INTRPT mode */

#define HSTPIPIFR_INTRPT_UNDERFIS_Pos 2

#define HSTPIPIFR_INTRPT_UNDERFIS     (_U_(0x1) << HSTPIPIFR_INTRPT_UNDERFIS_Pos)

#define HSTPIPIFR_INTRPT_RXSTALLDIS_Pos 6

#define HSTPIPIFR_INTRPT_RXSTALLDIS     (_U_(0x1) << HSTPIPIFR_INTRPT_RXSTALLDIS_Pos)

#define HSTPIPIFR_INTRPT_Msk          _U_(0x44)

/* -------- HSTPIPIMR : (USBHS Offset: 0x5c0) (R/ 32) Host Pipe Mask Register -------- */


#define HSTPIPIMR_OFFSET              (0x5C0)

#define HSTPIPIMR_RXINE_Pos           0

#define HSTPIPIMR_RXINE               (_U_(0x1) << HSTPIPIMR_RXINE_Pos)

#define HSTPIPIMR_TXOUTE_Pos          1

#define HSTPIPIMR_TXOUTE              (_U_(0x1) << HSTPIPIMR_TXOUTE_Pos)

#define HSTPIPIMR_PERRE_Pos           3

#define HSTPIPIMR_PERRE               (_U_(0x1) << HSTPIPIMR_PERRE_Pos)

#define HSTPIPIMR_NAKEDE_Pos          4

#define HSTPIPIMR_NAKEDE              (_U_(0x1) << HSTPIPIMR_NAKEDE_Pos)

#define HSTPIPIMR_OVERFIE_Pos         5

#define HSTPIPIMR_OVERFIE             (_U_(0x1) << HSTPIPIMR_OVERFIE_Pos)

#define HSTPIPIMR_SHORTPACKETIE_Pos   7

#define HSTPIPIMR_SHORTPACKETIE       (_U_(0x1) << HSTPIPIMR_SHORTPACKETIE_Pos)

#define HSTPIPIMR_NBUSYBKE_Pos        12

#define HSTPIPIMR_NBUSYBKE            (_U_(0x1) << HSTPIPIMR_NBUSYBKE_Pos)

#define HSTPIPIMR_FIFOCON_Pos         14

#define HSTPIPIMR_FIFOCON             (_U_(0x1) << HSTPIPIMR_FIFOCON_Pos)

#define HSTPIPIMR_PDISHDMA_Pos        16

#define HSTPIPIMR_PDISHDMA            (_U_(0x1) << HSTPIPIMR_PDISHDMA_Pos)

#define HSTPIPIMR_PFREEZE_Pos         17

#define HSTPIPIMR_PFREEZE             (_U_(0x1) << HSTPIPIMR_PFREEZE_Pos)

#define HSTPIPIMR_RSTDT_Pos           18

#define HSTPIPIMR_RSTDT               (_U_(0x1) << HSTPIPIMR_RSTDT_Pos)

#define HSTPIPIMR_Msk                 _U_(0x750BB)

/* CTRL mode */

#define HSTPIPIMR_CTRL_TXSTPE_Pos     2

#define HSTPIPIMR_CTRL_TXSTPE         (_U_(0x1) << HSTPIPIMR_CTRL_TXSTPE_Pos)

#define HSTPIPIMR_CTRL_RXSTALLDE_Pos  6

#define HSTPIPIMR_CTRL_RXSTALLDE      (_U_(0x1) << HSTPIPIMR_CTRL_RXSTALLDE_Pos)

#define HSTPIPIMR_CTRL_Msk            _U_(0x44)

/* ISO mode */

#define HSTPIPIMR_ISO_UNDERFIE_Pos    2

#define HSTPIPIMR_ISO_UNDERFIE        (_U_(0x1) << HSTPIPIMR_ISO_UNDERFIE_Pos)

#define HSTPIPIMR_ISO_CRCERRE_Pos     6

#define HSTPIPIMR_ISO_CRCERRE         (_U_(0x1) << HSTPIPIMR_ISO_CRCERRE_Pos)

#define HSTPIPIMR_ISO_Msk             _U_(0x44)

/* BLK mode */

#define HSTPIPIMR_BLK_TXSTPE_Pos      2

#define HSTPIPIMR_BLK_TXSTPE          (_U_(0x1) << HSTPIPIMR_BLK_TXSTPE_Pos)

#define HSTPIPIMR_BLK_RXSTALLDE_Pos   6

#define HSTPIPIMR_BLK_RXSTALLDE       (_U_(0x1) << HSTPIPIMR_BLK_RXSTALLDE_Pos)

#define HSTPIPIMR_BLK_Msk             _U_(0x44)

/* INTRPT mode */

#define HSTPIPIMR_INTRPT_UNDERFIE_Pos 2

#define HSTPIPIMR_INTRPT_UNDERFIE     (_U_(0x1) << HSTPIPIMR_INTRPT_UNDERFIE_Pos)

#define HSTPIPIMR_INTRPT_RXSTALLDE_Pos 6

#define HSTPIPIMR_INTRPT_RXSTALLDE     (_U_(0x1) << HSTPIPIMR_INTRPT_RXSTALLDE_Pos)

#define HSTPIPIMR_INTRPT_Msk          _U_(0x44)

/* -------- HSTPIPIER : (USBHS Offset: 0x5f0) (/W 32) Host Pipe Enable Register -------- */


#define HSTPIPIER_OFFSET              (0x5F0)

#define HSTPIPIER_RXINES_Pos          0

#define HSTPIPIER_RXINES              (_U_(0x1) << HSTPIPIER_RXINES_Pos)

#define HSTPIPIER_TXOUTES_Pos         1

#define HSTPIPIER_TXOUTES             (_U_(0x1) << HSTPIPIER_TXOUTES_Pos)

#define HSTPIPIER_PERRES_Pos          3

#define HSTPIPIER_PERRES              (_U_(0x1) << HSTPIPIER_PERRES_Pos)

#define HSTPIPIER_NAKEDES_Pos         4

#define HSTPIPIER_NAKEDES             (_U_(0x1) << HSTPIPIER_NAKEDES_Pos)

#define HSTPIPIER_OVERFIES_Pos        5

#define HSTPIPIER_OVERFIES            (_U_(0x1) << HSTPIPIER_OVERFIES_Pos)

#define HSTPIPIER_SHORTPACKETIES_Pos  7

#define HSTPIPIER_SHORTPACKETIES      (_U_(0x1) << HSTPIPIER_SHORTPACKETIES_Pos)

#define HSTPIPIER_NBUSYBKES_Pos       12

#define HSTPIPIER_NBUSYBKES           (_U_(0x1) << HSTPIPIER_NBUSYBKES_Pos)

#define HSTPIPIER_PDISHDMAS_Pos       16

#define HSTPIPIER_PDISHDMAS           (_U_(0x1) << HSTPIPIER_PDISHDMAS_Pos)

#define HSTPIPIER_PFREEZES_Pos        17

#define HSTPIPIER_PFREEZES            (_U_(0x1) << HSTPIPIER_PFREEZES_Pos)

#define HSTPIPIER_RSTDTS_Pos          18

#define HSTPIPIER_RSTDTS              (_U_(0x1) << HSTPIPIER_RSTDTS_Pos)

#define HSTPIPIER_Msk                 _U_(0x710BB)

/* CTRL mode */

#define HSTPIPIER_CTRL_TXSTPES_Pos    2

#define HSTPIPIER_CTRL_TXSTPES        (_U_(0x1) << HSTPIPIER_CTRL_TXSTPES_Pos)

#define HSTPIPIER_CTRL_RXSTALLDES_Pos 6

#define HSTPIPIER_CTRL_RXSTALLDES     (_U_(0x1) << HSTPIPIER_CTRL_RXSTALLDES_Pos)

#define HSTPIPIER_CTRL_Msk            _U_(0x44)

/* ISO mode */

#define HSTPIPIER_ISO_UNDERFIES_Pos   2

#define HSTPIPIER_ISO_UNDERFIES       (_U_(0x1) << HSTPIPIER_ISO_UNDERFIES_Pos)

#define HSTPIPIER_ISO_CRCERRES_Pos    6

#define HSTPIPIER_ISO_CRCERRES        (_U_(0x1) << HSTPIPIER_ISO_CRCERRES_Pos)

#define HSTPIPIER_ISO_Msk             _U_(0x44)

/* BLK mode */

#define HSTPIPIER_BLK_TXSTPES_Pos     2

#define HSTPIPIER_BLK_TXSTPES         (_U_(0x1) << HSTPIPIER_BLK_TXSTPES_Pos)

#define HSTPIPIER_BLK_RXSTALLDES_Pos  6

#define HSTPIPIER_BLK_RXSTALLDES      (_U_(0x1) << HSTPIPIER_BLK_RXSTALLDES_Pos)

#define HSTPIPIER_BLK_Msk             _U_(0x44)

/* INTRPT mode */

#define HSTPIPIER_INTRPT_UNDERFIES_Pos 2

#define HSTPIPIER_INTRPT_UNDERFIES     (_U_(0x1) << HSTPIPIER_INTRPT_UNDERFIES_Pos)

#define HSTPIPIER_INTRPT_RXSTALLDES_Pos 6

#define HSTPIPIER_INTRPT_RXSTALLDES     (_U_(0x1) << HSTPIPIER_INTRPT_RXSTALLDES_Pos)

#define HSTPIPIER_INTRPT_Msk          _U_(0x44)

/* -------- HSTPIPIDR : (USBHS Offset: 0x620) (/W 32) Host Pipe Disable Register -------- */


#define HSTPIPIDR_OFFSET              (0x620)

#define HSTPIPIDR_RXINEC_Pos          0

#define HSTPIPIDR_RXINEC              (_U_(0x1) << HSTPIPIDR_RXINEC_Pos)

#define HSTPIPIDR_TXOUTEC_Pos         1

#define HSTPIPIDR_TXOUTEC             (_U_(0x1) << HSTPIPIDR_TXOUTEC_Pos)

#define HSTPIPIDR_PERREC_Pos          3

#define HSTPIPIDR_PERREC              (_U_(0x1) << HSTPIPIDR_PERREC_Pos)

#define HSTPIPIDR_NAKEDEC_Pos         4

#define HSTPIPIDR_NAKEDEC             (_U_(0x1) << HSTPIPIDR_NAKEDEC_Pos)

#define HSTPIPIDR_OVERFIEC_Pos        5

#define HSTPIPIDR_OVERFIEC            (_U_(0x1) << HSTPIPIDR_OVERFIEC_Pos)

#define HSTPIPIDR_SHORTPACKETIEC_Pos  7

#define HSTPIPIDR_SHORTPACKETIEC      (_U_(0x1) << HSTPIPIDR_SHORTPACKETIEC_Pos)

#define HSTPIPIDR_NBUSYBKEC_Pos       12

#define HSTPIPIDR_NBUSYBKEC           (_U_(0x1) << HSTPIPIDR_NBUSYBKEC_Pos)

#define HSTPIPIDR_FIFOCONC_Pos        14

#define HSTPIPIDR_FIFOCONC            (_U_(0x1) << HSTPIPIDR_FIFOCONC_Pos)

#define HSTPIPIDR_PDISHDMAC_Pos       16

#define HSTPIPIDR_PDISHDMAC           (_U_(0x1) << HSTPIPIDR_PDISHDMAC_Pos)

#define HSTPIPIDR_PFREEZEC_Pos        17

#define HSTPIPIDR_PFREEZEC            (_U_(0x1) << HSTPIPIDR_PFREEZEC_Pos)

#define HSTPIPIDR_Msk                 _U_(0x350BB)

/* CTRL mode */

#define HSTPIPIDR_CTRL_TXSTPEC_Pos    2

#define HSTPIPIDR_CTRL_TXSTPEC        (_U_(0x1) << HSTPIPIDR_CTRL_TXSTPEC_Pos)

#define HSTPIPIDR_CTRL_RXSTALLDEC_Pos 6

#define HSTPIPIDR_CTRL_RXSTALLDEC     (_U_(0x1) << HSTPIPIDR_CTRL_RXSTALLDEC_Pos)

#define HSTPIPIDR_CTRL_Msk            _U_(0x44)

/* ISO mode */

#define HSTPIPIDR_ISO_UNDERFIEC_Pos   2

#define HSTPIPIDR_ISO_UNDERFIEC       (_U_(0x1) << HSTPIPIDR_ISO_UNDERFIEC_Pos)

#define HSTPIPIDR_ISO_CRCERREC_Pos    6

#define HSTPIPIDR_ISO_CRCERREC        (_U_(0x1) << HSTPIPIDR_ISO_CRCERREC_Pos)

#define HSTPIPIDR_ISO_Msk             _U_(0x44)

/* BLK mode */

#define HSTPIPIDR_BLK_TXSTPEC_Pos     2

#define HSTPIPIDR_BLK_TXSTPEC         (_U_(0x1) << HSTPIPIDR_BLK_TXSTPEC_Pos)

#define HSTPIPIDR_BLK_RXSTALLDEC_Pos  6

#define HSTPIPIDR_BLK_RXSTALLDEC      (_U_(0x1) << HSTPIPIDR_BLK_RXSTALLDEC_Pos)

#define HSTPIPIDR_BLK_Msk             _U_(0x44)

/* INTRPT mode */

#define HSTPIPIDR_INTRPT_UNDERFIEC_Pos 2

#define HSTPIPIDR_INTRPT_UNDERFIEC     (_U_(0x1) << HSTPIPIDR_INTRPT_UNDERFIEC_Pos)

#define HSTPIPIDR_INTRPT_RXSTALLDEC_Pos 6

#define HSTPIPIDR_INTRPT_RXSTALLDEC     (_U_(0x1) << HSTPIPIDR_INTRPT_RXSTALLDEC_Pos)

#define HSTPIPIDR_INTRPT_Msk          _U_(0x44)

/* -------- HSTPIPINRQ : (USBHS Offset: 0x650) (R/W 32) Host Pipe IN Request Register -------- */


#define HSTPIPINRQ_OFFSET             (0x650)

#define HSTPIPINRQ_INRQ_Pos           0

#define HSTPIPINRQ_INRQ               (_U_(0xFF) << HSTPIPINRQ_INRQ_Pos)

#define HSTPIPINRQ_INMODE_Pos         8

#define HSTPIPINRQ_INMODE             (_U_(0x1) << HSTPIPINRQ_INMODE_Pos)

#define HSTPIPINRQ_Msk                _U_(0x1FF)

/* -------- HSTPIPERR : (USBHS Offset: 0x680) (R/W 32) Host Pipe Error Register -------- */


#define HSTPIPERR_OFFSET              (0x680)

#define HSTPIPERR_DATATGL_Pos         0

#define HSTPIPERR_DATATGL             (_U_(0x1) << HSTPIPERR_DATATGL_Pos)

#define HSTPIPERR_DATAPID_Pos         1

#define HSTPIPERR_DATAPID             (_U_(0x1) << HSTPIPERR_DATAPID_Pos)

#define HSTPIPERR_PID_Pos             2

#define HSTPIPERR_PID                 (_U_(0x1) << HSTPIPERR_PID_Pos)

#define HSTPIPERR_TIMEOUT_Pos         3

#define HSTPIPERR_TIMEOUT             (_U_(0x1) << HSTPIPERR_TIMEOUT_Pos)

#define HSTPIPERR_CRC16_Pos           4

#define HSTPIPERR_CRC16               (_U_(0x1) << HSTPIPERR_CRC16_Pos)

#define HSTPIPERR_COUNTER_Pos         5

#define HSTPIPERR_COUNTER             (_U_(0x3) << HSTPIPERR_COUNTER_Pos)

#define HSTPIPERR_Msk                 _U_(0x7F)

#define HSTPIPERR_CRC_Pos             4

#define HSTPIPERR_CRC                 (_U_(0x1) << HSTPIPERR_CRC_Pos)

/* -------- CTRL : (USBHS Offset: 0x800) (R/W 32) General Control Register -------- */


#define CTRL_OFFSET                   (0x800)

#define CTRL_RDERRE_Pos               4

#define CTRL_RDERRE                   (_U_(0x1) << CTRL_RDERRE_Pos)

#define CTRL_VBUSHWC_Pos              8

#define CTRL_VBUSHWC                  (_U_(0x1) << CTRL_VBUSHWC_Pos)

#define CTRL_FRZCLK_Pos               14

#define CTRL_FRZCLK                   (_U_(0x1) << CTRL_FRZCLK_Pos)

#define CTRL_USBE_Pos                 15

#define CTRL_USBE                     (_U_(0x1) << CTRL_USBE_Pos)

#define CTRL_UID_Pos                  24

#define CTRL_UID                      (_U_(0x1) << CTRL_UID_Pos)

#define CTRL_UIMOD_Pos                25

#define CTRL_UIMOD                    (_U_(0x1) << CTRL_UIMOD_Pos)

#define   CTRL_UIMOD_HOST_Val         _U_(0x0)

#define   CTRL_UIMOD_DEVICE_Val       _U_(0x1)

#define CTRL_UIMOD_HOST               (CTRL_UIMOD_HOST_Val << CTRL_UIMOD_Pos)

#define CTRL_UIMOD_DEVICE             (CTRL_UIMOD_DEVICE_Val << CTRL_UIMOD_Pos)

#define CTRL_Msk                      _U_(0x300C110)

/* -------- SR : (USBHS Offset: 0x804) (R/ 32) General Status Register -------- */


#define SR_OFFSET                     (0x804)

#define SR_RDERRI_Pos                 4

#define SR_RDERRI                     (_U_(0x1) << SR_RDERRI_Pos)

#define SR_SPEED_Pos                  12

#define SR_SPEED                      (_U_(0x3) << SR_SPEED_Pos)

#define   SR_SPEED_FULL_SPEED_Val     _U_(0x0)

#define   SR_SPEED_HIGH_SPEED_Val     _U_(0x1)

#define   SR_SPEED_LOW_SPEED_Val      _U_(0x2)

#define SR_SPEED_FULL_SPEED           (SR_SPEED_FULL_SPEED_Val << SR_SPEED_Pos)

#define SR_SPEED_HIGH_SPEED           (SR_SPEED_HIGH_SPEED_Val << SR_SPEED_Pos)

#define SR_SPEED_LOW_SPEED            (SR_SPEED_LOW_SPEED_Val << SR_SPEED_Pos)

#define SR_CLKUSABLE_Pos              14

#define SR_CLKUSABLE                  (_U_(0x1) << SR_CLKUSABLE_Pos)

#define SR_Msk                        _U_(0x7010)

/* -------- SCR : (USBHS Offset: 0x808) (/W 32) General Status Clear Register -------- */


#define SCR_OFFSET                    (0x808)

#define SCR_RDERRIC_Pos               4

#define SCR_RDERRIC                   (_U_(0x1) << SCR_RDERRIC_Pos)

#define SCR_Msk                       _U_(0x10)

/* -------- SFR : (USBHS Offset: 0x80c) (/W 32) General Status Set Register -------- */


#define SFR_OFFSET                    (0x80C)

#define SFR_RDERRIS_Pos               4

#define SFR_RDERRIS                   (_U_(0x1) << SFR_RDERRIS_Pos)

#define SFR_VBUSRQS_Pos               9

#define SFR_VBUSRQS                   (_U_(0x1) << SFR_VBUSRQS_Pos)

#define SFR_Msk                       _U_(0x210)

typedef struct

{

  __IO uint32_t DEVDMANXTDSC;

  __IO uint32_t DEVDMAADDRESS;

  __IO uint32_t DEVDMACONTROL;

  __IO uint32_t DEVDMASTATUS;

} devdma_t;


typedef struct

{

  __IO uint32_t HSTDMANXTDSC;

  __IO uint32_t HSTDMAADDRESS;

  __IO uint32_t HSTDMACONTROL;

  __IO uint32_t HSTDMASTATUS;

} hstdma_t;


typedef struct

{

  __IO uint32_t DEVCTRL;

  __I  uint32_t DEVISR;

  __O  uint32_t DEVICR;

  __O  uint32_t DEVIFR;

  __I  uint32_t DEVIMR;

  __O  uint32_t DEVIDR;

  __O  uint32_t DEVIER;

  __IO uint32_t DEVEPT;

  __I  uint32_t DEVFNUM;

  __I  uint8_t                        Reserved1[220];

  __IO uint32_t DEVEPTCFG[10];

  __I  uint8_t                        Reserved2[8];

  __I  uint32_t DEVEPTISR[10];

  __I  uint8_t                        Reserved3[8];

  __O  uint32_t DEVEPTICR[10];

  __I  uint8_t                        Reserved4[8];

  __O  uint32_t DEVEPTIFR[10];

  __I  uint8_t                        Reserved5[8];

  __I  uint32_t DEVEPTIMR[10];

  __I  uint8_t                        Reserved6[8];

  __O  uint32_t DEVEPTIER[10];

  __I  uint8_t                        Reserved7[8];

  __O  uint32_t DEVEPTIDR[10];

  __I  uint8_t                        Reserved8[200];

       devdma_t DEVDMA[7];

  __I  uint8_t                        Reserved9[128];

  __IO uint32_t HSTCTRL;

  __I  uint32_t HSTISR;

  __O  uint32_t HSTICR;

  __O  uint32_t HSTIFR;

  __I  uint32_t HSTIMR;

  __O  uint32_t HSTIDR;

  __O  uint32_t HSTIER;

  __IO uint32_t HSTPIP;

  __IO uint32_t HSTFNUM;

  __IO uint32_t HSTADDR1;

  __IO uint32_t HSTADDR2;

  __IO uint32_t HSTADDR3;

  __I  uint8_t                        Reserved10[208];

  __IO uint32_t HSTPIPCFG[10];

  __I  uint8_t                        Reserved11[8];

  __I  uint32_t HSTPIPISR[10];

  __I  uint8_t                        Reserved12[8];

  __O  uint32_t HSTPIPICR[10];

  __I  uint8_t                        Reserved13[8];

  __O  uint32_t HSTPIPIFR[10];

  __I  uint8_t                        Reserved14[8];

  __I  uint32_t HSTPIPIMR[10];

  __I  uint8_t                        Reserved15[8];

  __O  uint32_t HSTPIPIER[10];

  __I  uint8_t                        Reserved16[8];

  __O  uint32_t HSTPIPIDR[10];

  __I  uint8_t                        Reserved17[8];

  __IO uint32_t HSTPIPINRQ[10];

  __I  uint8_t                        Reserved18[8];

  __IO uint32_t HSTPIPERR[10];

  __I  uint8_t                        Reserved19[104];

       hstdma_t HSTDMA[7];

  __I  uint8_t                        Reserved20[128];

  __IO uint32_t CTRL;

  __I  uint32_t SR;

  __O  uint32_t SCR;

  __O  uint32_t SFR;

} dcd_registers_t;


#define USB_REG           ((dcd_registers_t *)0x40038000U)

#define EP_MAX            10


#define FIFO_RAM_ADDR     0xA0100000u


// Errata: The DMA feature is not available for Pipe/Endpoint 7

#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)


#else // TODO : SAM3U


#endif


#endif /* _COMMON_USB_REGS_H_ */

dcd_registers_t
USBHS hardware registers.
Definition: common_usb_regs.h:2028

dcd_registers_t::DEVEPT
__IO uint32_t DEVEPT
Definition: common_usb_regs.h:2036

dcd_registers_t::DEVIMR
__I uint32_t DEVIMR
Definition: common_usb_regs.h:2033

dcd_registers_t::DEVISR
__I uint32_t DEVISR
Definition: common_usb_regs.h:2030

dcd_registers_t::SCR
__O uint32_t SCR
Definition: common_usb_regs.h:2090

dcd_registers_t::DEVIFR
__O uint32_t DEVIFR
Definition: common_usb_regs.h:2032

dcd_registers_t::SR
__I uint32_t SR
Definition: common_usb_regs.h:2089

dcd_registers_t::DEVIER
__O uint32_t DEVIER
Definition: common_usb_regs.h:2035

dcd_registers_t::DEVIDR
__O uint32_t DEVIDR
Definition: common_usb_regs.h:2034

dcd_registers_t::HSTADDR1
__IO uint32_t HSTADDR1
Definition: common_usb_regs.h:2064

dcd_registers_t::DEVCTRL
__IO uint32_t DEVCTRL
Definition: common_usb_regs.h:2029

dcd_registers_t::HSTICR
__O uint32_t HSTICR
Definition: common_usb_regs.h:2057

dcd_registers_t::HSTIDR
__O uint32_t HSTIDR
Definition: common_usb_regs.h:2060

dcd_registers_t::HSTFNUM
__IO uint32_t HSTFNUM
Definition: common_usb_regs.h:2063

dcd_registers_t::DEVICR
__O uint32_t DEVICR
Definition: common_usb_regs.h:2031

dcd_registers_t::CTRL
__IO uint32_t CTRL
Definition: common_usb_regs.h:2088

dcd_registers_t::DEVFNUM
__I uint32_t DEVFNUM
Definition: common_usb_regs.h:2037

dcd_registers_t::HSTIFR
__O uint32_t HSTIFR
Definition: common_usb_regs.h:2058

dcd_registers_t::HSTIER
__O uint32_t HSTIER
Definition: common_usb_regs.h:2061

dcd_registers_t::HSTPIP
__IO uint32_t HSTPIP
Definition: common_usb_regs.h:2062

dcd_registers_t::HSTCTRL
__IO uint32_t HSTCTRL
Definition: common_usb_regs.h:2055

dcd_registers_t::SFR
__O uint32_t SFR
Definition: common_usb_regs.h:2091

dcd_registers_t::HSTIMR
__I uint32_t HSTIMR
Definition: common_usb_regs.h:2059

dcd_registers_t::HSTADDR2
__IO uint32_t HSTADDR2
Definition: common_usb_regs.h:2065

dcd_registers_t::HSTISR
__I uint32_t HSTISR
Definition: common_usb_regs.h:2056

dcd_registers_t::HSTADDR3
__IO uint32_t HSTADDR3
Definition: common_usb_regs.h:2066

devdma_t
DEVDMA hardware registers.
Definition: common_usb_regs.h:2010

devdma_t::DEVDMAADDRESS
__IO uint32_t DEVDMAADDRESS
Definition: common_usb_regs.h:2012

devdma_t::DEVDMACONTROL
__IO uint32_t DEVDMACONTROL
Definition: common_usb_regs.h:2013

devdma_t::DEVDMANXTDSC
__IO uint32_t DEVDMANXTDSC
Definition: common_usb_regs.h:2011

devdma_t::DEVDMASTATUS
__IO uint32_t DEVDMASTATUS
Definition: common_usb_regs.h:2014

hstdma_t
HSTDMA hardware registers.
Definition: common_usb_regs.h:2019

hstdma_t::HSTDMANXTDSC
__IO uint32_t HSTDMANXTDSC
Definition: common_usb_regs.h:2020

hstdma_t::HSTDMASTATUS
__IO uint32_t HSTDMASTATUS
Definition: common_usb_regs.h:2023

hstdma_t::HSTDMAADDRESS
__IO uint32_t HSTDMAADDRESS
Definition: common_usb_regs.h:2021

hstdma_t::HSTDMACONTROL
__IO uint32_t HSTDMACONTROL
Definition: common_usb_regs.h:2022